pt7a6527 Pericom Technology Inc, pt7a6527 Datasheet - Page 21

• Manufacturer Part Number: pt7a6527
• Description: Hdlc Controller
• Manufacturer: Pericom Technology Inc

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Table 7 State of PT7A6527 after a Hardware Reset
Register Name
Common
registers
Individual
registers
i = A, B, C, D
Initialization
The purpose of the initialization is to set the PT7A6527 into a
state where it is able to correctly transfer HDLC frames and to
manage collisions according to the requirements of the
application.
The initialization process is divided into two phases. First, the
common settings are determined via the registers CCR and
VISM. These registers determine the number of HDLC
Table 8 Initialization of PT7A6527 (common bits)
PT0080(02/09)
Configuration
Serial interface characteristics
Interrupt configuration
HDLC address
recognition features
Function
ACR
CCR
VISR
VISM
ISTA
ISM
STAR
CMDR
MODE
RFBC
TSR
Value after Hardware
Reset (hex)
00
00
00
00
00
00
52
00
00
00
00
Register
VISM
CCR
CCR
CCR
ACR
SCG, SCS, SCP
MDS1-0
MIC3-0
AC0-3
SCM
ODS
BNS
CRS
Bits
VIS
Meaning
Address comparison disabled.
Single connection TS mode.
Interrupt vector may be read on AD bus bits 0 - 3.
Bits per frame: 256.
Bit rate is equal to clock rate.
Output drivers are of the push-pull type.
No interrupt from any PT7A6527 channel.
All channel interrupts are enabled.
No interrupts from channel i.
All channel i interrupts enabled.
Transmit FIFO is ready to be written. Receive line is idle. 1.3 version
No commands.
Test loop not active.
No collisions will be detected (unconditional transmission).
Inter-frame time fill = idle.
Receiver de-activated.
Channel i disabled (high impedance output).
Channel capacity is 2 bits/time slot.
Zero bytes received.
Time slot 0 selected.
21
channels used, the serial interface configuration and common
characteristics of the serial input/output connections (table 8).
Secondly, each of the HDLC channels is initialized via its own
register set as shown in table 11. The optional address
comparison mode for each HDLC channel is selected by
programming the ACR register, located in the common
address space (table 8).
Basic configuration and timing mode
Output driver type is open-drain or push pull
Clock rate = 1 or 2 x data rate
Number of bits per PCM frame
Mask any HDLC channel(s)
VISR may be read on AD bus bits 0-3 or 4-7
Address compare mode: accept/reject
Selection of compare addresses
Address compare on/off for HDLC channel 0, 1, 2, 3
Effect
HDLC controller
Data Sheet
PT7A6527
Ver:4