pt7a4402b Pericom Technology Inc, pt7a4402b Datasheet - Page 9

• Manufacturer Part Number: pt7a4402b
• Description: T1/e1 System Synchronizer
• Manufacturer: Pericom Technology Inc

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Output Interface Circuit
The Output Interface Circuit consists of the Tapped Delay Lines
and E1/T1 Dividers as shown in Figure 5.
Signals from the DCO are sent to Tapped Delay Lines to gener-
ate two clock signals, 16.384MHz and 12.352MHz, which are
divided in the T1 and E1 Dividers respectively to provide needed
clock and frame signals.
The T1 Divider uses the 12.352MHz signal to generate two
clock signals, C1.5 and C3. They have a nominal 50% duty
cycle.
PT0100(12/05)
Figure 4. Block Diagram of DPLL
Figure 5. Block Diagram of Output Interface Circuit
Reference
Corrector
from TIE
Virtual
Frequency Select MUX
Feedback Signal
Detector
Phase
From
DCO1
Signal
Signal
DCO2
From
From
Limiter
Tapped
Tapped
Delay
State Select From
Input Impairment
Delay
Line
Line
Monitor
Control Circuit
12MHz
16MHz
9
Filter
Loop
The E1 Divider uses the 16.384MHz signal to generate four
clock signals and three frame signals, i.e., C2, C4, C8, C16, F0,
F8 and F16. The frame signals are generated directly from the
C16 signal.
The C2, C4, C16 and C8 signals have nominal 50% duty cycle.
All the frame and clock outputs are locked to each other for all
operating states. They have limited driving capability and
should be buffered when driving high capacitance loads.
State Machine
State Select
Divider
Divider
From
T1
E1
T1/E1 System Synchronizer
DCO
C1.5
C3
C2
C4
C8
C16
F0
F8
F16
PT7A4402B/4402L
DPLL Reference
Output Interface
Circuit
to
Data Sheet
Ver:1