pt7a4408 Pericom Technology Inc, pt7a4408 Datasheet - Page 9

• Manufacturer Part Number: pt7a4408
• Description: T1/e1/oc3 System Synchronizer
• Manufacturer: Pericom Technology Inc

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Mode Controller
The Mode Controller determines whether the PT7A4408/
4408L operates in Normal or Free-Run state.
All state changes are synchronous with the rising edge of F8.
See the Modes of Operation section for complete details.
APLL
The analog PLL is intended to be used to achieve a 50% Duty
cycle output clock. Connecting C19 to ACKi will generate a
phase locked 19.44 MHz ACKo output with a nominal 50%
duty cycle and a maximum peak-to-peak unfiltered jitter of
0.174 U.I. . The analog PLL has an intrinsic jitter of less than
0.01 U.I. In order to achieve this low jitter level separate pins
are provided to power (AVDD, AGND) the APLL.
Modes of Operation
The PT7A4408/4408L operates in Normal or Free-Run con-
trolled by pin MS.
Normal State
In Normal State, the PT7A4408/4408L output signals are syn-
chronized with input reference.
In this state, the input reference signal is used as reference for
the DPLL phase detector.
Free-Run State
Typically the Free-Run State is used when a master clock is
required or immediately following system power-up before
network synchronization is achieved.
In Free-Run State, the outputs of the PT7A4408/4408L are
uncorrelated with the input reference signal and the stored
information of output reference. Instead, these output signals
are based solely on the master clock frequency (OSCi). The
accuracy of the output clock is equal to the accuracy of the
master clock (OSCi).
PT0106(09/02)
MS = 0: Normal
MS = 1: Freerun
9
Applications Information
Master Clock
The PT7A4408/4408L uses either an external clock source or
an external crystal as the master timing source.
In Free-Run State, the frequency tolerance of the PT7A4408/
4408L output clocks are equal to the frequency tolerance of
the timing source. In an application, if an accurate Free-Run
State is not required, the tolerance of the master timing source
may be 100ppm. If required, the tolerance must be no greater
than 32ppm.
The capture range of PT7A4408/4408L will also be consid-
ered when deciding the accuracy of the master timing source.
The sum of the accuracy of the master timing source and the
capture range of the PT7A4408/4408L will always equal
230ppm. For example, if the master timing source is 100ppm,
the capture range will be 130ppm.
• Clock Oscillator
If using an external clock source, its output pin should be
connected directly (not AC coupled) to the OSCi pin of the
PT7A4408/4408L and the OSCo pin of PT7A4408/4408L can
be left open as shown in Figure 5 or connected as an output
pin.
When selecting the clock oscillator, following specifications
should be considered. They are
Refer to AC Electrical Characteristics.
Figure 5. Clock Oscillator Connection
- absolute frequency
- frequency change over temperature
- output rise and fall time
- output level
- duty cycle
PT7A4408/4408L
T1/E1/OC3 System Synchronizer
OSCo
No Connection
OSCi
20MHz OUT
+5V
GND
+5V
PT7A4408/4408L
Data Sheet
0.1 F
Ver:0