pt7a4410 Pericom Technology Inc, pt7a4410 Datasheet
pt7a4410
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pt7a4410 Summary of contents
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... ETSI ETS 300 011 in jitter tolerance, jitter transfer, intrinsic jitter, frequency accuracy, hold- over accuracy, capture range, phase slope and MTIE, etc. The PT7A4410/4410L operates in Manual or Auto- matic Mode, and in each of the modes, three operat- ing states are available: Normal, Holdover and Free- Run. ...
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... Overall Operation ................................................................................................................................. 7 Modes and States of Operation ........................................................................................................... 10 Applications Information .................................................................................................................... 14 Detailed Specifications .............................................................................................................................. 16 Definitions of Critical Performance Specifictions ............................................................................... 16 Absolute Maximum Ratings ............................................................................................................... 18 Recommended Operating Conditions ................................................................................................. 18 DC Electrical and Power Supply Characteristics ................................................................................ 19 AC Electrical Characteristics .............................................................................................................. 20 Mechanical Specifications ......................................................................................................................... 33 Note .......................................................................................................................................................... 34 PT0106(09/02) T1/E1/OC3 System Synchronizer Contents 2 Data Sheet PT7A4410/4410L Ver:0 ...
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... GND TCLR CC Virtual Reference TIE DPLL Corrector State State Select Select Input Impairment Monitor Guard Time Circuit MS2 GTo GTi 3 Data Sheet PT7A4410/4410L ACKi APLL ACKo C1 Output C6 Interface C8 Circuit C16 C19 F0 F8 F16 RSP TSP Feedback Frequency Select MUX FS1 ...
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... PLCC Top View 4 Data Sheet PT7A4410/4410L ...
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... Data Sheet PT7A4410/4410L ...
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... Data Sheet PT7A4410/4410L ...
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... Referring to the block diagram on Page 3, the detailed func- tions of the PT7A4410/4410L are described as follows. Master Clock The PT7A4410/4410L uses either an external clock source or an external crystal and a few discrete components with its internal oscillator as the master clock. Reference Select MUX The PT7A4410/4410L accepts two independent reference sig- nals, the primary reference and secondary reference ...
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... ETS 300- 011 and AT&T TR62411 are met. Loop Limiter Filter Control Circuit State Select From State Select Input Impairment From Monitor State Machine 8 Data Sheet PT7A4410/4410L DPLL Reference to DCO Output Interface Circuit Ver:0 ...
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... Tapped Delay Line in the Output Interface Circuit to produce 12.352MHz, 12.624MHz, 19.44MHz and 16.384MHz signals. The DCO synchronization method depends upon the PT7A4410/4410L operating state, as follows: In Normal state, the DCO generates four output signals which are frequency and phase locked to the selected input reference signal ...
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... U.I. In order to achieve this low jitter level separate pins are provided to power (AVDD, AGND) the APLL. Modes and States of Operation The PT7A4410/4410L operates either in Manual mode or Au- tomatic mode. Each mode has three possible operating states, Normal, Holdover or Free-Run. Shown in Table 4 and Table 5 are the mode and state selection instructions, using pins MS1, MS2, and RSEL ...
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... Typically the Free-Run State is used when a master clock is required or immediately following system power-up before network synchronization is achieved. In Free-Run State, the outputs of the PT7A4410/4410L are uncorrelated with the input reference signal and the stored information of output reference. Instead, these output signals are based solely on the master clock frequency (OSCi). The accuracy of the output clock is equal to the accuracy of the master clock (OSCi) ...
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... S2A S1A Auto-Holdover Secondary Primary (001) (000) S2H S1H Holdover Holdover Secondary Primary (011) (010) * Movement to Normal State from any state requires a valid input signal. 12 Data Sheet PT7A4410/4410L ...
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... Auto-Holdover Primary Secondary (X0X) (011) (X0X) (011) (010 or 11X) S2H S1H Holdover Holdover Secondary Primary * Movement to Normal State from any state requires a valid input signal. 13 Data Sheet PT7A4410/4410L ...
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... If the PRI signal re- turns to normal before the expiration of the guard time (level at GTi pin is low), the PT7A4410/4410L will return to Normal State with PRI input reference. If the PRI signal is still de- graded after expiration of the guard time (level at GTi be- comes high), the reference switching (from PRI to SEC) will occur ...
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... The timing diagram is shown in Figure 13. Figure 12. Unsymmetrical Guard Time Circuit PT7A4410/4410L GTo + GTi Good Bad Good Bad PRI PRI PRI Holdover Normal Holdover 15 Data Sheet PT7A4410/4410L R C 150k + Good SEC PRI Normal Normal Ver:0 ...
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... C3 0.1 F For the PT7A4410/4410L, two internal elements determine the jitter attenuation. They are internal 1.9Hz low pass loop filter and phase slope limiter. The phase slope limiter limits the output phase slope to 5ns/125 s. Therefore, if the input ...
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... PT7A4410/4410L does not affect Holdover accuracy, but the change in OSCi accuracy while in Holdover Mode does. Lock Range: If the PT7A4410/4410L DPLL is already in a state of synchronization (“lock”) with the incoming reference signal able to track this signal to maintain lock as its frequency varies over a certain range, called the Lock Range ...
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... Data Sheet PT7A4410/4410L ...
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... and V measurement Data Sheet PT7A4410/4410L ...
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... Data Sheet PT7A4410/4410L * ...
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... Timing Reference Points 21 Data Sheet PT7A4410/4410L ...
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... Data Sheet PT7A4410/4410L ...
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... Data Sheet PT7A4410/4410L ...
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... R15D R2D Data Sheet PT7A4410/4410L ...
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... PT0106(09/02) T1/E1/OC3 System Synchronizer t F0WL t C16WL t t C8W C8W t C4W t C4W t C2W t C3W t C15W t C6W C6W t C19W t C19W t RSPD t TSPW t TSPD 25 Data Sheet PT7A4410/4410L t F8WH F0D F16D t F16WL C16D C8D C4D C2D C3D ...
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... Data Sheet PT7A4410/4410L ...
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... Data Sheet PT7A4410/4410L ...
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... Data Sheet PT7A4410/4410L ...
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... For Free-Run State of ±100ppm. 18. For capture range of ±230ppm. 19. For capture range of ±198ppm. 20. For capture range of ±130ppm. 21. 25pF capacitive load. PT0106(09/02) PT7A4410/4410L T1/E1/OC3 System Synchronizer 22. OSCi Master Clock Jitter is less than 2ns p-p, or 0.04UI p-p where 1UI p-p = 1/20MHz. 23. Jitter on reference input is less than 7ns p-p. 24. Applied jitter is sinusoidal. ...
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... Mechanical Specifications Figure 21. 44-pin PLCC PT0106(09/02) PT7A4410/4410L T1/E1/OC3 System Synchronizer 33 Data Sheet Ver:0 ...
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... Pericom Technology product. The company makes no representations that circuitry described herein is free from patent infringement or other rights, of Pericom Technology Incorporation. PT0106(09/02) T1/E1/OC3 System Synchronizer Note Pericom Technology Inc. Web-Site: www.pti.com.cn, www.pti-ic.com Fax: (86)-21-6485 2181 Fax: (852)- 2243 3667 Fax: (1)-408-435 1100 34 Data Sheet PT7A4410/4410L Ver:0 ...