pt7a8980 Pericom Technology Inc, pt7a8980 Datasheet - Page 6

• Manufacturer Part Number: pt7a8980
• Description: Pt7a8980/8980l Digital Switch
• Manufacturer: Pericom Technology Inc

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PT0011(12/05)
Functional Description
ST-BUS (Serial Telecom Bus) is widely used in bus architecture.
It supports digital voice, data switching and inter-processor
communication within the Telecommunication Switch or Ac-
cess System. The ST-BUS data stream has a bit rate of 2048
kbit/s. It
32 channels, and each channel contains one byte of serial data.
The PT7A8980/8980L is designed to handle data in the ST-BUS
format. It combines data switching function and inter-proces-
sor communication function into one device. Therefore, it
suitable for use in distributed processing systems to switch
digitized voice or data in ST-BUS format.
The PT7A8980/8980L can perform the data switching between
channels on ST-BUS input and channels on ST-BUS output.
The microprocessor can read the data from any ST-BUS input
channel or write the data to any ST-BUS output channel via the
microprocessor interface . The microprocessor communicates
with the PT7A8980/8980L in the same way as with its external
memory. By writing to the PT7A8980/8980L, the microproces-
sor can either establish switched connections between one ST-
BUS input channel and one ST-BUS output channel or transmit
specific messages to ST-BUS output channels. On the other
hand, by reading from the PT7A8980/8980L, the microproces-
sor can receive messages from ST-BUS input channel or check
which switching connections have been already established.
Input and Output Control
2048 kbit/s ST-BUS data goes to the chip through 8 ST-BUS
inputs (STi0-STi7) of the PT7A8980/8980L. Each ST-BUS input
data stream contains 32 channels, each channel contains 8 bits.
After entering into the chip, the 8 bit data is converted into
parallel form, and is stored in one of the 256 x 8 Voice or Data
Memory locations. Each byte location in the Data Memory is
associated with a channel on one of the 8 ST-BUS input data
streams.
Similarly, each location of 256 x 11 Connection Memory is also
associated with a channel on one of the ST-BUS output data
streams . The Connection Memory is divided into two parts,
high and low. In each memory location, the high part contains 3
bits, the low part contains 8 bits. When a data is due to be
transmitted to a ST-BUS output, the data of the channel can
either be switched from a ST-BUS input channel or can origi-
nate from the microprocessor. If the data is switched from an
channel, the contents of the Connection Memory Low Loca-
tion associated with the output channel will be used to address
the Data Memory. Since this Data Memory address corresponds
to a specific channel on a ST-BUS input stream, the
’
s organized in frames of 125 s. Each frame contains
’
s
6
data from this input channel is switched to be put out to the
proper output channel. If the data to an output channel origi-
nates from the microprocessor (Message Mode), the contents
of the Connection Memory Low Location associated with the
output channel are output directly, and this data is output re-
petitively on the channel every frame until the microprocessor
intervenes.
Microprocessor Interface and Address Selection
The Microprocessor Interface consists of data lines D7-D0,
address lines A5-A0 and control signals CS, DTA . The micro-
processor can access the Control Register as well as the memory
inside the chip via the Microprocessor Interface. There are two
parts of any address of the Data Memory and Connection
Memory. The higher 3 bits come from the Control Register, and
the lower 5 bits come from the address lines directly.
As shown in Table 3 above, whether the processor access the
Control Register or the internal memory depends on the status
of address line A5. If A5 is 0, the Control Register is addressed
regardless of the value of the other address lines. If A5 is 1, the
internal memory is addressed. In this case, the contents of the
Control Register bits 4~3 determine whether Connection
Memory High or Low or Data Memory is accessed. The Control
Register bits 2~0 select the memory address associated with
the particular data stream, while address lines A4~A0 select the
memory location corresponding to the channel of this data
stream.
Table 3. Address Memory Map
*
* *
A5
A5
A5
o
A5
A
0
1
1
1
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.
.
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A4
A4
A4
A
m
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x
0
0
1
.
.
.
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PT7A8980/8980L Digital Switch
A3
A3
A3
A3
A
l o
x
0
0
a
1
.
.
.
e h
3
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C
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A2
A2
A2
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A
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0
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1
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.
.
.
2
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r t
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S
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A1
A1
A1
A
r t
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0
0
R
1
.
.
.
1
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m
s i
A0
A0
A0
A0
A
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x
0
1
1
.
.
.
a
0
e r
i r
t s
p s
A
0
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c e
H x e
H x e
H x e
H x e
H
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1 2
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