73m2901ce Maxim Integrated Products, Inc., 73m2901ce Datasheet - Page 14

• Manufacturer Part Number: 73m2901ce
• Description: V.22bis Single Chip Modem
• Manufacturer: Maxim Integrated Products, Inc.

73M2901CE Data Sheet
DS_2901CE_031
6 Design Considerations
The 73M2901CE single chip modem includes all the basic modem functions. Programmable configuration
options make this device highly adaptable to a wide variety of applications.
Unlike digital logic circuitry, modem designs must contend with precise frequency tolerances and verify
low-level analog signals to ensure acceptable performance. Using good analog circuit design practices
will generally result in a sound design. The crystal oscillator should be held to a 50 ppm tolerance. The
recommendations in this section should be taken into consideration when starting new designs.
6.1
Layout Considerations
Good analog/digital design rules must be used to control system noise in order to obtain high
performance in modem designs. The more digital circuitry present in the application, the more attention
to noise control is needed.
High speed, digital devices should be locally bypassed, and the telephone line interface and the modem
should be located next to each other near where the telephone line connection is accessed. It is
recommended that power supplies and ground traces be routed separately to the analog and digital portions
on the board. Digital signals should not be routed near low-level or high impedance analog traces.
The 73M2901CE should be considered a high performance analog device. A 3.3 µF electrolytic capacitor in
parallel with a 0.1 µF Ceramic capacitor should be placed between each VPD and VND pin and a 10 µF and
0.1 µF between VPA and VNA. A 0.1 µF ceramic capacitor should be placed between VREF and VNA as
well as between VBG and VNA. Use of ground planes and large traces on power is recommended.
Keep OSCIN and OSCOUT signals as short as possible and locate the crystal near the pins. Use an
11.0592 MHz parallel mode crystal only. Do not use ground planes under the oscillator circuit since this
will increase the parasitic capacitance on the pins. The values of C2 and C3 depend on the load
capacitance rating of the crystal that is used, not the 73M2901CE. This load capacitance will typically be
between 15 pF and 27 pF, but usually 18 or 22 pF. Parallel resonant crystals are tuned with a specific
capacitive load and will be within their specifications when this load is used. This rating is the
capacitance measured between the crystal pins including all parasitic capacitances. It is not the values of
the capacitors used. The selection of these capacitors can vary with the layout of the PCB, so do not
assume the values used with the 73M2901CE demo board are correct for all designs.
System noise is the most likely cause of poor Caller ID and low-level receive performance. The lowest
amplitude signals that the modem will need to receive are on the order of 5 mV rms. The Caller ID
receive levels are also very low due to the requirement to have a high (60 kΩ) AC input impedance while
on hook. Having a 20 dB gain boost during Caller ID reception compensates for this, but if there is
excessive noise, it will also be amplified. Keeping the analog and digital grounds separate helps control
the amount of noise that gets to the receiver input. Dramatic improvements in low-level performance can
be gained by proper layout.
Keep the VCC trace as short as possible. Make the power trace a minimum of 0.5 mm thick. The analog
and digital power and ground should be kept separate for best low receive level performance. Route the
power to the digital pins and bypass capacitors on one net and the analog power and VBG bypass pins
on another net with inductors separating the two. If power planes are used, separate the power and
ground planes so there are separate analog and digital planes for the 73M2901CE.
Keep all analog signaling away from any high-speed digital circuitry and traces that may be on the board.
Observe the separation of the network and modem side circuitry. Maintain at least ¼ inch (6 mm)
separation between the two. Do not run power planes under the network side circuitry and maintain the
same spacing for the planes from the network. Use only UL, CSA, or TUV approved components that
cross the isolation barrier or for network protection to assure compliant performance for the DAA.
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