wm8762ged-v Wolfson Microelectronics plc, wm8762ged-v Datasheet - Page 10

• Manufacturer Part Number: wm8762ged-v
• Description: 24-bit 192khz Stereo Dac
• Manufacturer: Wolfson Microelectronics plc

WM8762
CLOCKING SCHEMES
DIGITAL AUDIO INTERFACE
AUDIO DATA SAMPLING RATES
w
Figure 6 Left Justified Mode Timing Diagram
Table 1 Master Clock Frequencies Versus Sampling Rate
In a typical digital audio system there is only one central clock source producing a reference
clock to which all audio data processing is synchronised. This clock is often referred to as the
audio system’s Master Clock. The external master clock can be applied directly through the
MCLK input pin with no configuration necessary for sample rate selection.
Note that on the WM8762, MCLK is used to derive clocks for the DAC path. The DAC path
consists of DAC sampling clock, DAC digital filter clock and DAC digital audio interface timing.
In a system where there are a number of possible sources for the reference clock it is
recommended that the clock source with the lowest jitter be used to optimise the performance
of the DAC.
The device can be powered down by stopping MCLK. In this state the power consumption is
substantially reduced.
WM8762 supports the left justified audio interface format. The WM8762 supports word lengths
of 16-24 bits (MSB first). The word length may be any value up to 24-bits. (If the word length
shorter than 24-bits is used, the unused bits will be padded with zeros).
In left justified mode, the MSB of DIN is sampled by the WM8762 on the first rising edge of
BCKIN following a LRCIN transition. LRCIN is high during the left samples and low during the
right samples.
The master clock for WM8762 supports audio sampling rates from 128fs to 768fs, where fs is
the audio sampling frequency (LRCIN) typically 32kHz, 44.1kHz, 48kHz, 96kHz or 192kHz. The
master clock is used to operate the digital filters and the noise shaping circuits.
The WM8762 has a master clock detection circuit that automatically determines the relation
between the master clock frequency and the sampling rate (to within +/- 8 master clocks). If
there is a greater than 8 clocks error, the interface shuts down the DAC and mutes the output.
The master clock should be synchronised with LRCIN, although the WM8762 is tolerant of
phase differences or jitter on this clock.
SAMPLING
LRCIN
44.1kHz
BCKIN
(LRCIN)
192kHz
32kHz
48kHz
96kHz
RATE
DIN
MSB
1
5.6448
24.576
2
12.288
4.096
6.114
128fs
3
LEFT CHANNEL
18.432
36.864
n-2 n-1
6.144
8.467
9.216
MASTER CLOCK FREQUENCY (MHZ) (MCLK)
192fs
n
LSB
Unavailable
11.2896
12.288
24.576
8.192
256fs
MSB
1/fs
1
2
3
Unavailable
16.9340
12.288
18.432
36.864
384fs
RIGHT CHANNEL
n-2 n-1
Unavailable
Unavailable
PD, Rev 4.4, January 2009
22.5792
16.384
24.576
n
LSB
512fs
Production Data
Unavailable
Unavailable
33.8688
24.576
36.864
768fs
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