wm8594seft-v Wolfson Microelectronics plc, wm8594seft-v Datasheet - Page 45

• Manufacturer Part Number: wm8594seft-v
• Description: 24-bit 192khz 2vrms Multi-channel Codec
• Manufacturer: Wolfson Microelectronics plc

Production Data
POP AND CLICK PERFORMANCE
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The WM8594 includes a number of features designed to minimise pops and clicks in various phases
of operation including power up, power down, changing analogue paths and starting/stopping clocks.
In order to ensure optimum performance, the following sequences should be followed.
POWERUP SEQUENCE
1.
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3.
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9.
Apply power to the WM8594 (see Power On Reset).
Set-up initial internal biases:
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Enable output drivers to allow the AC coupling capacitors at the output stage to be pre-
charged to DACVMID:
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Enable DACVMID. 750kΩ selected here for optimum pop reduction:
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Wait until DACVMID has fully charged. The time is dependent on the capacitor values
used to AC-couple the outputs and to decouple DACVMID, and the VMID_SEL value
chosen.
resistance and C is the decoupling capacitor on DACVMID. For DACVMID resistance of
50kΩ and C=4.7uF, the delay should be approximately 1.5 seconds.
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Enable the master bias:
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Switch the output drivers to use the master bias instead of the power up (fast) bias:
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Enable all functions (DACs, ADC, PGAs) required for use. PGAs are muted by default so
the write order is not important.
Unmute the PGAs and switch DACVMID resistance to 75k for normal operation:
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SOFT_ST=1
FAST_EN=1
POBCTRL=1
BUFIO_EN=1
VOUTxL_EN=1
VOUTxR_EN=1
VMID_SEL=10
Insert delay
BIAS_EN=1
POBCTRL=0
PGAxL_MUTE=0
PGAxR_MUTE=0
VMID_SEL=01
An approximate delay of 6xRCms can be used, where R is the DACVMID
PD Rev 4.1 July 2008
WM8594
45