CD4069UBCN Fairchild Semiconductor, CD4069UBCN Datasheet
CD4069UBCN
Specifications of CD4069UBCN
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CD4069UBCN Summary of contents
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... Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow CD4069UBCSJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide CD4069UBCN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Device also available in Tape and Reel. Specify by appending suffix “X” to the ordering code. ...
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Absolute Maximum Ratings (Note 2) DC Supply Voltage ( Input Voltage ( Storage Temperature Range ( Power Dissipation ( Dual-In-Line Small Outline Lead Temperature ( (Soldering, 10 ...
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AC Electrical Characteristics pF, R 200 and Symbol Parameter Propagation Delay Time from PHL PLH Input to Output Transition Time THL ...
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Typical Performance Characteristics Gate Transfer Characteristics Power Dissipation vs. Frequency Propagation Delay Time vs. Load Capacitance www.fairchildsemi.com Propagation Delay vs. Ambient Temperature Propagation Delay vs. Ambient Temperature 4 ...
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Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M14A 5 www.fairchildsemi.com ...
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide www.fairchildsemi.com Package Number M14D 6 ...
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right ...