tp5335 Supertex, Inc., tp5335 Datasheet

tp5335

Manufacturer Part Number

tp5335

Description

P-channel Enhancement-mode Vertical Dmos Fet

Manufacturer

Supertex, Inc.

Datasheet

1.TP5335.pdf (3 pages)

Current page: 1 of 3
Download datasheet (448Kb)

Features

►

Applications

►

-G indicates package is RoHS compliant (‘Green’)

Absolute Maximum Ratings

Absolute Maximum Ratings are those values beyond which damage to the device

may occur. Functional operation under these conditions is not implied. Continuous

operation of the device at the absolute rating level may affect device reliability. All

voltages are referenced to device ground.

* Distance of 1.6mm from case for 10 seconds.

Ordering Information

Parameter

Drain-to-source voltage

Drain-to-gate voltage

Gate-to-source voltage

Operating and storage temperature

Soldering temperature*

TP5335

Device

High input impedance and high gain

Low power drive requirement

Ease of paralleling

Low C

Excellent thermal stability

Integral source-drain diode

Free from secondary breakdown

Complementary N- and P-channel devices

Logic level interfaces - ideal for TTL and CMOS

Solid state relays

Analog switches

Power management

Telecom switches

ISS

and fast switching speeds

TO-236AB (SOT-23)

Package Option

TP5335K1-G

P-Channel Enhancement-Mode

Vertical DMOS FET

-55

C to +150

DSS

-350

(V)

/BV

300

Value

±20V

DGS

DSS

General Description

The Supertex TP5335 is a low threshold enhancement-

mode (normally-off) transistor utilizing an advanced vertical

DMOS structure and Supertex’s well-proven silicon-gate

manufacturing process. This combination produces a device

with the power handling capabilities of bipolar transistors

and the high input impedance and positive temperature

coefﬁ cient inherent in MOS devices. Characteristic of all

MOS structures, this device is free from thermal runaway

and thermally-induced secondary breakdown.

Supertex’s vertical DMOS FETs are ideally suited to a

wide range of switching and amplifying applications where

high breakdown voltage, high input impedance, low input

capacitance, and fast switching speeds are desired.

Pin Conﬁ guration

Product Marking Information

(max)

DS(ON)

(Ω)

P3SW

(max)

TO-236AB (SOT-23) (K1)

-2.4

GS(TH)

(V)

DRAIN

W = Code for week sealed

GATE

= “Green” Packaging

SOURCE

TP5335

Related parts for tp5335

tp5335 Summary of contents

Page 1

... Distance of 1.6mm from case for 10 seconds. P-Channel Enhancement-Mode Vertical DMOS FET General Description The Supertex TP5335 is a low threshold enhancement- mode (normally-off) transistor utilizing an advanced vertical DMOS structure and Supertex’s well-proven silicon-gate manufacturing process. This combination produces a device with the power handling capabilities of bipolar transistors and the high input impedance and positive temperature coefﬁ ...

Page 2

... 1MHz -25V -150mA 25Ω, GEN PULSE GENERATOR R GEN INPUT TP5335 I † DRM (mA) (mA) -85 -400 = -100µ -1.0mA D = -1.0mA 125 -330V DS = -25V DS = -25V DS = -150mA D = -200mA ...

Page 3

... MAX 1.12 0.10 JEDEC Registration TO-236, Variation AB, Issue H, Jan. 1999. Drawings not to scale. (The package drawing(s) in this data sheet may not reﬂ ect the most current speciﬁ cations. For the latest package outline information go to http://www.supertex.com/packaging.html.) Doc.# DSFP-TP5335 A102607 ...

Related keywords

tp5335 datasheet
tp5335 data sheet
tp5335 pdf datasheet
tp5335 component
tp5335 part
tp5335 distributor
tp5335 RoHS
tp5335 datasheet download