net2890 ETC-unknow, net2890 Datasheet - Page 39

• Manufacturer Part Number: net2890
• Description: Interface Controller
• Manufacturer: ETC-unknow

Specification
5.3 Base Registers
5.3.1 (Address 00h; PAGESEL) Paged Register Select
5.3.2 (Address 01h; MAINCTL) Main Control Register
5.3.3 (Address 02h; DMACTL) DMA Control Register
Bits
Bits
Bits
____________________________________________________________________________________
7:5
4:0
7:5
7:5
2:0
4
3
2
1
0
4
3
Description
Paged Register Set select. These bits select one of the paged sets of configuration
registers. The select value pages one of the sets of registers into the address range
10-1F. All values not listed below are Reserved.
Value
0h
1h
2h
3h
4h
7h
Reserved
Description
Reserved
Retry Enable. If set, this bit enables the automatic retry feature. If an error occurs
during an IN packet, the same packet data is transmitted when the next IN token is
received. If an error occurs during an OUT packet, the corresponding FIFO is
flushed. No interrupts or status bits will change as a result of failed packets. Note that
isochronous endpoints are never retried.
Device Remote Wake-up Enable. If set, this bit enables the WAKEUP# pin to cause
a device remote wake-up.
Device Configured. When the NET2890 has been successfully configured by the
host, the local CPU can set this bit which causes the DEVCFG# output pin to be
asserted. This bit is cleared when a root port reset is detected.
Power Good. When the PWRGOOD# pin is asserted, this bit is read as a one,
indicating that the local power supply is operational.
Self Powered. When the BUSPWR# pin is negated (high), this bit is read as a one,
indicating that the NET2890 is operating in the self powered mode.
Description
Reserved
DMA Request. This status bit reflects the state of the DRQ output pin, and allows a
CPU on the local bus to monitor DMA transfers.
DMA Request Enable. Writing a 1 to this bit causes the NET2890 to start
requesting DMA cycles from a DMA controller on the local bus. If the EOT# input is
asserted, this bit is automatically reset. A CPU on the local bus may also explicitly
reset this bit to terminate a DMA transfer.
If the CPU sets the FIFO Valid bit of the endpoint selected by field 2:0, this bit is
cleared. This bit can be read to determine whether a DMA transfer is still in progress.
DMA Endpoint Select. This field determines which Endpoint is being accessed
during a DMA transfer. 000 = Endpoint 0, 001 = A, 010 = B, 011 = C, 100 = D.
Paged Register Set
Endpoint 0 (Control)
Endpoint A
Endpoint B
Endpoint C
Endpoint D
Setup Packet Registers
335 Pioneer Way, Mountain View, California 94041
TEL [phone] FAX [phone]
NetChip Technology, Inc., 1999
Rev 2.0, Draft 9, July 16, 1999
http://www.netchip.com
NET2890 USB Interface Controller
Read
Read
Read
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Write
Write
Write
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
Default
Default
Default
Value
Value
Value
0
0
0
1
0
0
0
0
0
0
0
0
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