74HC02D,653 NXP Semiconductors, 74HC02D,653 Datasheet

IC GATE NOR QUAD 2INPUT 14SOIC

74HC02D,653

Manufacturer Part Number
74HC02D,653
Description
IC GATE NOR QUAD 2INPUT 14SOIC
Manufacturer
NXP Semiconductors
Series
74HCr
Datasheet

Specifications of 74HC02D,653

Number Of Circuits
4
Package / Case
14-SOIC (3.9mm Width), 14-SOL
Logic Type
NOR Gate
Number Of Inputs
2
Current - Output High, Low
5.2mA, 5.2mA
Voltage - Supply
2 V ~ 6 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Product
NOR
Logic Family
HC
High Level Output Current
- 5.2 mA
Low Level Output Current
5.2 mA
Propagation Delay Time
7 ns
Supply Voltage (max)
6 V
Supply Voltage (min)
2 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Logical Function
NOR
Number Of Elements
4
Operating Supply Voltage (typ)
5V
Operating Temp Range
-40C to 125C
Package Type
SO
Number Of Outputs
1
Technology
CMOS
Mounting
Surface Mount
Pin Count
14
Operating Temperature Classification
Automotive
Quiescent Current
2uA
Operating Supply Voltage (max)
6V
Operating Supply Voltage (min)
2V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
568-1381-2
74HC02D-T
933714150653

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
74HC02D,653
Manufacturer:
NXP
Quantity:
10 000
Part Number:
74HC02D,653
Manufacturer:
NXP
Quantity:
500
1. General description
2. Features
3. Ordering information
Table 1.
Type number
74HC02N
74HCT02N
74HC02D
74HCT02D
74HC02DB
74HCT02DB
74HC02PW
74HCT02PW
74HC02BQ
74HCT02BQ
Ordering information
Package
Temperature range
40 C to +125 C
40 C to +125 C
40 C to +125 C
40 C to +125 C
40 C to +125 C
The 74HC02; 74HCT02 are high-speed Si-gate CMOS devices that comply with JEDEC
standard no. 7A. They are pin compatible with Low-power Schottky TTL (LSTTL).
The 74HC02; 74HCT02 provides a quad 2-input NOR function.
I
I
I
I
74HC02; 74HCT02
Quad 2-input NOR gate
Rev. 03 — 18 September 2008
Input levels:
ESD protection:
Multiple package options
Specified from 40 C to +85 C and from 40 C to +125 C
N
N
N
N
For 74HC02: CMOS level
For 74HCT02: TTL level
HBM JESD22-A114E exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Name
DIP14
SO14
SSOP14
TSSOP14
DHVQFN14
Description
plastic dual in-line package; 14 leads (300 mil)
plastic small outline package; 14 leads; body width
3.9 mm
plastic shrink small outline package; 14 leads; body
width 5.3 mm
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 14 terminals;
body 2.5
3
0.85 mm
Product data sheet
Version
SOT27-1
SOT108-1
SOT337-1
SOT402-1
SOT762-1

Related parts for 74HC02D,653

74HC02D,653 Summary of contents

Page 1

Quad 2-input NOR gate Rev. 03 — 18 September 2008 1. General description The 74HC02; 74HCT02 are high-speed Si-gate CMOS devices that comply with JEDEC standard no. 7A. They are pin compatible with Low-power Schottky TTL (LSTTL). The ...

Page 2

... NXP Semiconductors 4. Functional diagram mna216 Fig 1. Logic symbol 5. Pinning information 5.1 Pinning GND Fig 4. Pin configuration DIP14, SO14 and (T)SSOP14 5.2 Pin description Table 2. Pin description Symbol Pin 10 9,12 GND 74HC_HCT02_3 Product data sheet 001aah084 Fig 2. IEC logic symbol 001aac919 Fig 5 ...

Page 3

... NXP Semiconductors 6. Functional description [1] Table 3. Function table Input [ HIGH voltage level LOW voltage level don’t care. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter V supply voltage ...

Page 4

... NXP Semiconductors Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V) Symbol Parameter t/ V input transition rise and fall rate 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 74HC02 V HIGH-level V = 2.0 V ...

Page 5

... NXP Semiconductors Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 74HCT02 V HIGH-level input voltage V LOW-level input voltage V HIGH-level output voltage 4 LOW-level output voltage 5.2 mA input leakage current supply current 6 additional per input pin; ...

Page 6

... NXP Semiconductors Table 7. Dynamic characteristics GND = pF; for load circuit see L Symbol Parameter Conditions 74HCT02 t propagation delay nA nY; see transition time power dissipation per package; PD capacitance V = GND [ the same as t and PHL PLH [ the same as t and THL TLH [ used to determine the dynamic power dissipation (P ...

Page 7

... NXP Semiconductors Test data is given in Table Definitions test circuit termination resistance should be equal to output impedance load capacitance including jig and probe capacitance. L Fig 7. Load circuitry for measuring switching times Table 9. Test data Type Input V I 74HC02 V CC 74HCT02 3.0 V 74HC_HCT02_3 Product data sheet ...

Page 8

... NXP Semiconductors 12. Package outline DIP14: plastic dual in-line package; 14 leads (300 mil pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions UNIT max. min. max. mm 4.2 0.51 3.2 inches 0.17 0.02 0.13 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. ...

Page 9

... NXP Semiconductors SO14: plastic small outline package; 14 leads; body width 3 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.01 0.069 0.004 0.049 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...

Page 10

... NXP Semiconductors SSOP14: plastic shrink small outline package; 14 leads; body width 5 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.21 1. 0.25 0.05 1.65 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION IEC SOT337-1 Fig 10. Package outline SOT337-1 (SSOP14) ...

Page 11

... NXP Semiconductors TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...

Page 12

... NXP Semiconductors DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...

Page 13

... Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Added type numbers 74HC02BQ and 74HCT02BQ (DHVQFN14 package) ...

Page 14

... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

Page 15

... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 Functional description . . . . . . . . . . . . . . . . . . . 3 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 5 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8 13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 13 14 Revision history ...

Related keywords