en5312q Enpirion, en5312q Datasheet - Page 11

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en5312q

Manufacturer Part Number
en5312q
Description
1a Synchronous Buck Regulator With Integrated Inductor
Manufacturer
Enpirion
Datasheet

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March 2007
Figure 6 shows an example schematic using an external voltage divider. VS0=VS1=VS2= “1”. The
resistor values are chosen to give an output voltage of 2.6V.
F
PCB top layer. Note the placement of the vias from the input and output filter capacitor grounds, and
the thermal pad, to the PCB ground on layer 2 (1
figure shows the layout with the components populated. Note the placement of the vias per
recommendation 3.
F
capacitor local grounds, and thermal pad, to PCB system ground.
Design Considerations for Lead-Frame Based Modules
Exposed Metal on Bottom Of Package
E
the electrical circuit. The lead frame offers many advantages in thermal performance, in reduced
electrical lead resistance, and in overall foot print. However, it does require some special
considerations.
A
support, some of the lead-frame cantilevers be exposed at the point where wire-bond or internal
passives are attached. This results in several small pads being exposed on the bottom of the
package.
O
connected to the PC board. The PCB top layer under the EN5312QI should be clear of any metal
except for the large thermal pad. The “grayed-out” area in Figure 8 represents the area that should
be clear of any metal (traces, vias, or planes), on the top layer of the PCB.
N
perimeter pins, meets or exceeds JEDEC requirements for lead frame package construction (J
MO-220, Issue J, Date May 2005). The separation between the large thermal pad and the nearest
adjacent metal pad or pin is a minimum of 0.20mm, including tolerances. This is shown in Figure 9.
©Enpirion 2007 all rights reserved, E&OE
igure 7. Example layout showing PCB top layer, as well as demonstrating use of vias from input, output filter
igure 7 shows an example board layout. The left side of the figure demonstrates construction of the
npirion has developed a break-through in package technology that utilizes the lead frame as part of
s part of the pa
OTE: Clearance between the various exposed metal pads, the thermal ground pad, and the
nly the
large thermal pad and the perimeter pin pads are to be mechanically or electrically
Thermal Vias to
Thermal Vias to
ckage assembly process, lead frame construction requires that for mechanical
Vias to Grou
Vias to Ground Plane
Ground Plane
Ground Plane
nd Plane
st
11
layer below PCB surface). The right side of the
C
C
IN
IN
C
C
OUT
OUT
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Package
Package
Outline
Outline
EN5312QI
EDEC

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