a2f500m3b-1csh484 Actel Corporation, a2f500m3b-1csh484 Datasheet - Page 61

• Manufacturer Part Number: a2f500m3b-1csh484
• Description: Actel
• Manufacturer: Actel Corporation

Figure 2-17 • Input Register Timing Diagram
Table 2-70 • Input Data Register Propagation Delays
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Note:
Enable
Data
Clear
CLK
Preset
Out_1
ICLKQ
ISUD
IHD
ISUE
IHE
ICLR2Q
IPRE2Q
IREMCLR
IRECCLR
IREMPRE
IRECPRE
IWCLR
IWPRE
ICKMPWH
ICKMPWL
For the derating values at specific junction temperature and voltage supply levels, refer to
for derating values.
Worst Commercial-Case Conditions: T
Input Register
Timing Characteristics
Clock-to-Q of the Input Data Register
Data Setup Time for the Input Data Register
Data Hold Time for the Input Data Register
Enable Setup Time for the Input Data Register
Enable Hold Time for the Input Data Register
Asynchronous Clear-to-Q of the Input Data Register
Asynchronous Preset-to-Q of the Input Data Register
Asynchronous Clear Removal Time for the Input Data Register
Asynchronous Clear Recovery Time for the Input Data Register
Asynchronous Preset Removal Time for the Input Data Register
Asynchronous Preset Recovery Time for the Input Data Register
Asynchronous Clear Minimum Pulse Width for the Input Data Register
Asynchronous Preset Minimum Pulse Width for the Input Data Register
Clock Minimum Pulse Width High for the Input Data Register
Clock Minimum Pulse Width Low for the Input Data Register
50%
50%
t
1
ISUE
t
IHE
50%
50%
t
ISUD
0
t
ICLKQ
t
IHD
50%
50%
50%
t
IWPRE
t
IPRE2Q
50%
Description
J
50%
= 85°C, Worst-Case VCC = 1.425 V
t
R e v i s i o n 3
IRECPRE
50%
t
ICLR2Q
50%
t
IWCLR
50%
50%
50%
Actel SmartFusion Intelligent Mixed Signal FPGAs
t
IRECCLR
50%
t
ICKMPWH
t
IREMPRE
50%
Table 2-7 on page 2-9
50%
t
ICKMPWL
0.27
0.38
0.46
0.46
0.00
0.00
0.23
0.36
0.32
0.24
0.00
0.00
0.23
0.22
0.22
–1
50%
t
50%
IREMCLR
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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