lfe3-150ea-8fn672itw Lattice Semiconductor Corp., lfe3-150ea-8fn672itw Datasheet - Page 108
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lfe3-150ea-8fn672itw
Manufacturer Part Number
lfe3-150ea-8fn672itw
Description
Latticeecp3 Family Data Sheet
Manufacturer
Lattice Semiconductor Corp.
Datasheet
1.LFE3-150EA-8FN672ITW.pdf
(136 pages)
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Figure 3-21. sysCONFIG Parallel Port Write Cycle
Figure 3-22. sysCONFIG Master Serial Port Timing
Figure 3-23. sysCONFIG Slave Serial Port Timing
WRITEN
1. In Master Parallel Mode the FPGA provides CCLK (MCLK). In Slave Parallel Mode the external device provides CCLK.
CCLK (output)
CCLK (input)
CCLK
CS1N
BUSY
D[0:7]
CSN
DOUT
1
DOUT
DIN
DIN
t
SUCBDI
t
t
SUWD
SUCS
Byte 0
t
t
SUSCDI
SUMCDI
t
BSCL
Byte 1
t
HCBDI
3-55
t
SSCL
Byte 2
t
DCB
t
BSCYC
t
BSCH
DC and Switching Characteristics
t
t
CODO
CODO
LatticeECP3 Family Data Sheet
t
SSCH
Byte n
t
t
HSCDI
HMCDI
t
HCS
t
HWD
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