rt9241 ETC-unknow, rt9241 Datasheet - Page 10

• Manufacturer Part Number: rt9241
• Description: Two-phase Dc/dc Controller For Cpu Core Power Supply
• Manufacturer: ETC-unknow

COMP
RT9241
The sensing circuit gets I
R
amplifier input bias current. I
just before low side MOSFET turns off (See Fig.2).
Therefore,
Droop Tuning
The S/H current signals from power channels are
injected to ADJ pin to create droop voltage.
The DAC output voltage decreases by V
the VCORE load droop(see Fig.3).
www.richtek-ic.com.tw
10
T
I
I
X
SP
X
V
OFF
S (
S (
ADJ
/
= R
/
) H
H
=
PWM Signal & High Side MOSFET Gate Signal
)
Fig. 2 Inductor Current and PWM Signal
=



=
=
SN
EA
V
R






I
V
I
L
IN
( L
ADJ
Low Side MOSFET Gate Signal
S (
_
DAC
V
to cancel the voltage drop caused by GM
AVG
−
IN
R
/
H
V
Falling Slope = V
×
Fig. 3 Droop Tune Circuit
SP
- V
)
FB
Inductor Current
O
)
×
2
3
−
ADJ



R
∑
×
V
S
+
5
O
I
µ
X
,
_
V
−
S
DAC
I
V



L
, for operating frequency = 200kHz
S (
ADJ
V
X
IN
/
V
=
) H
2
−
O
IN
L
I ×
=
L
V
/L
ADJ
R
R
X
∑
O
I
ADJ
SP
( L
R
is sampled and held



I
AVG
X
I
S
×
∑
L (S/H)
I
L
5
by local feedback.
µ
)
−
S






V
L
×
O
R
R
ADJ
×
I
L (AVG)
SP
S
T
OFF
2
to form
2/3 I
2/3 I
2/3 I
2/3 I
,
Preliminary
X1
X2
X3
X4
Protection and SS function
For OVP, the RT9241 detects the V
pin. Eliminate the parasitic delay and noise influence
on the PCB path for fast and accurate detection. The
trip point of OVP is 120% of normal output level. The
PWM outputs are pulled low to turn on the low side
MOSFET and turn off the high side MOSFET of the
synchronous rectifier at OVP. The OVP latch can
only be reset by VDD or DVD restart power on reset
sequence. The PGOOD detection trip point of V
is ±8% out of the normal level. The PGOOD open
drain output pulls low when V
range.
Soft start circuit generates a ramp voltage by
charging external capacitor with 10uA current after IC
POR acts. The PWM pulse width and V
clamped by the rising ramp to reduce the in-rush
current and protect the power devices.
Over current protection trip point is set by the resistor
R
channel S/H current signal I
forces PWM output latched at high impedance to turn
off both high and low side MOSFET in the power
stage and initial the hiccup mode protection. The SS
pin voltage is pulled low with a 10µA current after it is
less than 90% VDD. The converter restarts after SS
pin voltage < 0.2V. Three times of OCP disable the
converter and only release the latch by POR acts
(see Fig.4).
0A
4V
2V
0V
IMAX
V
COUNT = 1 COUNT = 2
connected to IMAX pin. OCP is triggered if one
CORE
I
L
T0T1
OVERLOAD
APPLIED
T2
Fig. 4
TIME
DS9241-00 November 2001
X
COUNT = 3
>
T3T4
3
2
OCRE
×
R
0
IMAX
CORE
6 .
SS
exceeds the
. Controller
CORE
by V
CORE
SEN
are