rt9259 Richtek Technology Corporation, rt9259 Datasheet - Page 9

• Manufacturer Part Number: rt9259
• Description: Synchronous Buck Dc-dc Linear Power Controller
• Manufacturer: Richtek Technology Corporation

(500mV/Div)
(500mV/Div)
Soft Start for Synchronous Buck Converter
A built-in soft-start is used to prevent surge current from
power supply input during power on (referring to the
Functional Block Diagram). The error amplifier EA is a three-
input device. SSE or V
the behavior non-inverting input. The internal soft start
voltage SSE linearly ramps up to about 4V after VIN1
existence is recognized with about 2ms delay. According,
the output voltage ramps up smoothly to its target level.
The rise time of output voltage is about 2ms as shown in
Figure 3. V
V
SSE is also used for LDO soft start. LDO input voltage
VIN2 MUST be ready before SSE starts to ramp up.
Otherwise UVP function of LDO may be triggered and shut
down the RT9259.
Under Voltage Protection
The voltages at FB and FBL pin are monitored for under
voltage protection (UVP) after the soft start is completed.
UVP is triggered if one of the feedback voltages is under
(50% x V
the RT9259 PWM controller is shut down when V
lower than the UVP threshold. In Figure 5, the RT9259
shuts down after 4 time UVP hiccups triggered by FBL.
DS9259-03T00 August 2007
RT_DIS
(20V/Div)
V
(10V/Div)
REF1
UGATE
LGATE
OUT1
.
REFX
REF1
) with a 30us delay. As shown in Figure 4,
Figure 3 : Start up by RT_DIS
takes over the behavior EA when SSE >
REF1
whichever is smaller dominates
Time (1ms/Div)
FB
drops
(500mV/Div)
(500mV/Div)
Over Current Protection
The RT9259 senses the current flowing through lower
MOSFET for over current protection (OCP) by sensing the
PHASE pin voltage as shown in the Functional Block
Diagram. A 40uA current source flows through internal 20kΩ
R
the resistor. OCP is triggered if the voltage at PHASE pin
(drop of lower MOSFET V
side MOSFET conducting. Accordingly inductor current
threshold for OCP is a function of conducting resistance
of lower MOSFET R
(20V/Div)
(20V/Div)
COMP
(10V/Div)
(20V/Div)
UGATE
OCSET
UGATE
I
FB
LGATE
(1V/Div)
V
OCSET
V
OUT
OUT1
to PHASE pin causes 0.8V voltage drop across
Figure 5. UVP hiccups triggered by FBL
=
40
Figure 4. UVP triggered by FB
μ
A
×
R
DS(ON)
OCSET
R
DS(ON)
DS
Time (10ms/Div)
Time (10ms/Div)
as :
) is lower than −0.4V when low
(20k
Ω
- )
0.4V
RT9259
www.richtek.com
V
IN1
=
= 12V to 0V
R
DS(ON)
0.4V
V
IN2
= 0V
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