adum3300 Analog Devices, Inc., adum3300 Datasheet - Page 8
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adum3300
Manufacturer Part Number
adum3300
Description
Triple-channel, Digital Isolators, Enhanced System-level Esd Reliability
Manufacturer
Analog Devices, Inc.
Datasheet
1.ADUM3300.pdf
(20 pages)
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ADuM3300/ADuM3301
Parameter
SWITCHING SPECIFICATIONS
For All Models
ADuM330xARW
ADuM330xBRW
ADuM330xCRW
90 Mbps (CRW Grade Only)
Input Currents
Minimum Pulse Width
Maximum Data Rate
Propagation Delay
Pulse-Width Distortion, |t
Propagation Delay Skew
Channel-to-Channel Matching,
Channel-to-Channel Matching,
Minimum Pulse Width
Maximum Data Rate
Propagation Delay
Pulse-Width Distortion, |t
Propagation Delay Skew
Channel-to-Channel Matching,
Channel-to-Channel Matching,
Minimum Pulse Width
Maximum Data Rate
Propagation Delay
Pulse-Width Distortion, |t
Propagation Delay Skew
Channel-to-Channel Matching
Opposing-Directional Channels
Codirectional Channels
Opposing-Directional Channels
V
Logic High Output Voltages
Logic Low Output Voltages
Change vs. Temperature
Codirectional Channels
Change vs. Temperature
V
Logic High Input Threshold
Logic Low Input Threshold
DD2
DD1
5 V/3 V Operation
3 V/5 V Operation
5 V/3 V Operation
3 V/5 V Operation
5 V/3 V Operation
3 V/5 V Operation
5 V/3 V Operation
3 V/5 V Operation
Supply Current
Supply Current
5
5
5
4
4
4
3
3
3
6
6
6
PLH
PLH
PLH
7
7
− t
− t
− t
7
PHL
PHL
PHL
|
|
|
5
7
5
7
5
Symbol
I
I
I
I
V
V
V
V
V
V
PW
t
PWD
t
t
PW
t
PWD
t
t
t
PW
t
PWD
t
t
t
DD1 (90)
DD2 (90)
IA
ID
PHL
PSK
PSKCD/OD
PHL
PSK
PSKCD
PSKOD
PHL
PSK
PSKCD
PSKOD
IH
IL
OAH
OCH
OAL,
OCL
, I
, I
, V
, V
, t
, t
, t
IB
E1
, V
, V
, V
V
, I
EL
, I
EH
PLH
PLH
PLH
OBL,
IC
ODL
ODH
E2
OBH
,
,
Rev. 0 | Page 8 of 20
V
V
Min
−10
2.0
1.6
1
50
10
15
90
20
DD1
DD1
, V
, V
DD2
DD2
− 0.1 V
− 0.4 V
Typ
41
22
15
28
+0.01
0.0
0.04
0.2
70
35
5
8.3
120
30
0.5
3
DD1
DD1
, V
, V
DD2
DD2
− 0.2
Max Unit
57
31
21
41
+10
0.8
0.4
0.1
0.1
0.4
1000 ns
100
40
50
50
100
50
3
22
3
6
11.1 ns
40
2
14
2
5
mA
mA
mA
mA
µA
V
V
V
V
V
V
V
V
V
Mbps
ns
ns
ns
ns
ns
Mbps
ns
ns
ps/°C
ns
ns
ns
Mbps
ns
ns
ps/°C
ns
ns
ns
Test Conditions
45 MHz logic signal freq.
45 MHz logic signal freq.
45 MHz logic signal freq.
45 MHz logic signal freq.
0 ≤ V
0 ≤ V
I
I
I
I
I
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
Ox
Ox
Ox
Ox
Ox
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= −20 µA, V
= −4 mA, V
= 20 µA, V
= 400 µA, V
= 4 mA, V
IA
E1
,V
,V
IB
E2
, V
≤ V
IC
,V
Ix
Ix
DD1
Ix
ID
= V
Ix
Ix
= V
= V
≤ V
= V
= V
or V
IxL
IxL
IxH
DD1
IxL
IxH
DD2
or V
DD2
,