sc480imltrt Semtech Corporation, sc480imltrt Datasheet - Page 14

• Manufacturer Part Number: sc480imltrt
• Description: Sc480 Complete Ddr1/2/3 Memory Power Supply
• Manufacturer: Semtech Corporation

Dropout Performance
The output voltage adjust range for continuous-conduction
operation is limited by the fi xed 400nS (typical) Minimum
Off-time One-shot. For best dropout performance, use the
slowest on-time setting of 200KHz. When working with
low input voltages, the duty-factor limit must be calculated
using worst-case values for on and off times. The IC duty-
factor limitation is given by:
Be sure to include inductor resistance and MOSFET on-
state voltage drops when performing worst-case dropout
duty-factor calculations.
SC480 System DC Accuracy (VDDQ Controller)
Three IC parameters affect VDDQ accuracy: the internal
1.5V reference, the error comparator offset voltage, and
the switching frequency variation with line and load.
The internal 1%, 1.5V reference contains two error
components, a 0.5% DC error and a 0.5% supply and
temperature error. The error comparator offset is trimmed
so that it trips when the feedback pin is nominally 1.5
volts +/-1% at room temperature. The comparator offset
trim compensates for any DC error in the reference. Thus,
the percentage error is the sum of the reference variation
over supply and temperature and the offset in the error
comparator, or 1.5% total.
The on-time pulse in the SC480 is calculated to give a
pseudo-fi xed frequency. Nevertheless, some frequency
variation with line and load can be expected. This variation
changes the output ripple voltage. Because constant on-
time converters regulate to the valley of the output ripple,
½ of the output ripple appears as a DC regulation error.
For example, If the output ripple is 50mV with VIN = 6
volts, then the measured DC output will be 25mV above
the comparator trip point. If the ripple increases to 80mV
with VIN = 25 volts, then the measured DC output will
be 40mV above the comparator trip. The best way to
minimize this effect is to minimize the output ripple.
To compensate for valley regulation it is often desirable
to use passive droop. Take the feedback directly from the
output side of the inductor, incorporating a small amount
© 2006 Semtech Corp.
POWER MANAGEMENT
POWER MANAGEMENT
Application Information (Cont.)
DUTY
TON
(MIN)
TON
(MIN)
TOFF
(MAX)
14
of trace resistance between the inductor and output
capacitor. This trace resistance should be optimized
so that at full load the output droops to near the lower
regulation limit. Passive droop minimizes the required
output capacitance because the voltage excursions due
to load steps are reduced.
Board components and layout also infl uence DC accuracy.
The use of 1% feedback resistors contributes up to 1%
error. If tighter DC accuracy is required use 0.1% feedback
resistors.
The output inductor value may change with current. This
will change the output ripple and thus the DC output
voltage (it will not change the frequency).
Switching frequency variation with load can be minimized
by choosing lower RDS
will cause the switching frequency to increase as the load
current increases. This will reduce the ripple and thus
the DC output voltage. This inherent droop should be
considered when deciding if passive droop is required, or
if passive droop is desired in order to further reduce the
output capacitance.
Output DC Accuracy (VTT Output)
The VTT accuracy compared to VDDQ is determined by
two parameters: the REF output accuracy, and the VTT
output accuracy with respect to REF. The REF output
is generated internally from the VDDQS (sense input),
and tracks VDDQS with 2% accuracy. This REF output
becomes the reference for the VTT regulator. The VTT
regulator then tracks REF within +/-40mV (typically zero).
The total VTT/VDDQ tracking accuracy is then:
DDR Reference Buffer
The reference buffer is capable of sourcing 10mA. The
reference buffer has a class A output stage and therefore
will not sink signifi cant current; there is an internal 50 kΩ
(typical) pulldown to ground. If higher current sinking is
required, an external pulldown resistor should be added.
Make sure that the ground side of this pulldown is tied to
the VTT ground plane near the PGND2 pin.
VTT
error
VDDQS
ON
2
MOSFETs. High RDS
0.02
40mV
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SC480
ON
MOSFETS