ox16pci958 Oxford Electrical Products, ox16pci958 Datasheet - Page 9

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ox16pci958

Manufacturer Part Number
ox16pci958
Description
Octal Uart With Interface
Manufacturer
Oxford Electrical Products
Datasheet

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3.2.
Table 6 summarizes the configuration and control registers for quick reference.
A
30h
31h
34h
40h
42h
4Ch
50h
EEPROM-Control Register
The OX16PCI958 automatically takes control of the EECS, EECK and EEDIO pins after a deassertion
of the host bus RESET signal, in order to read in configuration data. Afterwards, the signals may be
controlled though accesses to this register.
This register is set to 00h on a PCI reset.
DS-0022 Nov 05
Field (Bits)
EET2 (7)
EET1 (6)
EEDIO data in (4)
EECS (3)
EECK (2)
EEDIO output
enable (1)
EEDIO data out (0)
use
EEPROM-
control register
Power-
management
control register
UART interrupt
status (RO)
UART-enable
register
SISR enable
UART
configuration
Global pre-
divider
Configuration & Control Registers
Description
High—at least 70 PCI clock cycles have occurred since the register was last written.
Cleared when the register is written. Set to the value of EET1 every 70th PCI clock cycle.
This may be useful for ensuring that EEPROM timing constraints are met
Cleared when the register is written. Set every 70th PCI clock cycle
Returns the current logic level on the EEDIO pin.
Controls EECS output.
Controls EECK output
1—the value last written to bit 0 is driven on the EEDIO pin
0—EEDIO pin is tri-stated
Controls the logic level driven onto EEDIO when bit 1 is set.
Table 6 Configuration & Control Register Summary
D7
EET2
RFU
U7INT
U7EN
SEN
RFU1
RFU
D6
EET1
U6INT
U6EN
RFU1
External—Free Release
D5
RFU
PM_DRIVER
U5INT
U5EN
GCS1
1b
D4
EEDIO
data in
U4INT
U4EN
RFU1
D3
EECS
PM_LCLK
U3INT
U3EN
RFU
RFU
D2
EECK
U2INT
U2EN
GCS0
OX16PCI958 DATA SHEET
RFU
D1
EEDIO
output
enable
PM_OSC
U1INT
U1EN
RFU1
D0
EEDIO
data out
U0INT
U0EN
RFU
Page 9

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