ht82k70e-l Holtek Semiconductor Inc., ht82k70e-l Datasheet - Page 29

• Manufacturer Part Number: ht82k70e-l
• Description: I/o Type 8-bit Otp Mcu
• Manufacturer: Holtek Semiconductor Inc.

Standby Current Considerations
As the main reason for entering the Power Down Mode
is to keep the current consumption of the microcontroller
to as low a value as possible, perhaps only in the order
of several micro-amps, there are other considerations
which must also be taken into account by the circuit de-
signer if the power consumption is to be minimised.
Special attention must be made to the I/O pins on the
device. All high-impedance input pins must be con-
nected to either a fixed high or low level as any floating
input pins could create internal oscillations and result in
increased current consumption. Care must also be
taken with the loads, which are connected to I/O pins,
which are setup as outputs. These should be placed in a
condition in which minimum current is drawn or con-
nected only to external circuits that do not draw current,
such as other CMOS inputs.
If the configuration options have enabled the Watchdog
Timer internal oscillator then this will continue to run
when in the Power Down Mode and will thus consume
some power. For power sensitive applications it may be
therefore preferable to use the system clock source for
the Watchdog Timer.
Wake-up
After the system enters the Power Down Mode, it can be
woken up from one of various sources listed as follows:
If the system is woken up by an external reset, the de-
vice will experience a full system reset, however, if the
device is woken up by a WDT overflow, a Watchdog
Timer reset will be initiated. Although both of these
wake-up methods will initiate a reset operation, the ac-
tual source of the wake-up can be determined by exam-
ining the TO and PDF flags. The PDF flag is cleared by a
system power-up or executing the clear Watchdog
Timer instructions and is set when executing the HALT
instruction. The TO flag is set if a WDT time-out occurs,
and causes a wake-up that only resets the Program
Counter and Stack Pointer, the other flags remain in
their original status.
Configuration options determine which pin or groups of
pins can be setup to permit a negative transition on the
pin to wake-up the system. When a Port pin wake-up oc-
curs, the program will resume execution at the instruc-
tion following the HALT instruction.
Rev. 1.00
An external reset
An external falling edge on any of the I/O pins
A system interrupt
A WDT overflow
29
When a PA0/PA1 or PB0/PB1 wake up occurs, bits in
the WSR register can be read to know which pin
changed first.
If the system is woken up by an interrupt, then two possi-
ble situations may occur. The first is where the related
interrupt is disabled or the interrupt is enabled but the
stack is full, in which case the program will resume exe-
cution at the instruction following the HALT instruction.
In this situation, the interrupt which woke-up the device
will not be immediately serviced, but will rather be ser-
viced later when the related interrupt is finally enabled or
when a stack level becomes free. The other situation is
where the related interrupt is enabled and the stack is
not full, in which case the regular interrupt response
takes place. If an interrupt request flag is set to 1 be-
fore entering the Power Down Mode, the wake-up func-
tion of the related interrupt will be disabled.
No matter what the source of the wake-up event is, once
a wake-up situation occurs, a time period equal to 1024
system clock periods will be required before normal sys-
tem operation resumes. However, if the wake-up has
originated due to an interrupt, the actual interrupt sub-
routine execution will be delayed by an additional one or
more cycles. If the wake-up results in the execution of
the next instruction following the HALT instruction, this
will be executed immediately after the 1024 system
clock period delay has ended.
Low Voltage Detector - LVD
The Low Voltage Detector internal function provides a
means for the user to monitor when the power supply
voltage falls below a certain fixed level as specified in
the DC characteristics.
Operation
The LVD enable/disable control bit is bit 4 of the CTLR
register. Under normal operation, and when the power
supply voltage is above the specified VLVD value, spec-
ified by the LVD_sel bits in the CTLR register, the Low
battery bit will remain at a zero value. If the power supply
voltage should fall below this V
battery bit will change to a high value indicating a low
voltage condition. Note that the Low battery bit is a
read-only bit. By polling the Low battery bit in the CTLR
register, the application program can therefore deter-
mine the presence of a low voltage condition.
HT82K70E-L/HT82K76E-L
LVD
September 15, 2009
value then the Low