isplsi2096ve Lattice Semiconductor Corp., isplsi2096ve Datasheet - Page 9

• Manufacturer Part Number: isplsi2096ve
• Description: 3.3v In-system Programmable Superfast? High Density Pld
• Manufacturer: Lattice Semiconductor Corp.

Derivations of
Y0,1,2
GOE 0
ispLSI 2096VE Timing Model
Ded. In
I/O Pin
Reset
(Input)
t
t
t
Note: Calculations are based upon timing specifications for the ispLSI 2096VE-250L.
su
h
co
2.8ns
2.5ns
7.0ns
=
=
=
=
=
=
=
=
=
=
=
=
Logic + Reg su - Clock (min)
(
(#20 + #22 + #26) + (#29) - (#20 + #22 + #35)
(0.5 + 0.2 + 2.8) + (0.8) - (0.5 + 0.2 + 0.8)
Clock (max) + Reg h - Logic
(
(#20 + #22 + #35) + (#30) - (#20 + #22 + #26)
(0.5 + 0.2 + 3.6) + (1.7) - (0.5 + 0.2 + 2.8)
Clock (max) + Reg co + Output
(
(#20 + #22 + #35) + (#31) + (#36 + #38)
(0.5 + 0.2 + 3.6) + (0.2) + (1.1 + 1.4)
I/O Delay
t
t
t
io +
io +
io +
#21
#20
t
I/O Cell
su,
t
t
t
grp +
grp +
grp +
t
h and
t
t
t
20ptxor) + (
ptck(max)) + (
ptck(max)) + (
t
co from the Product Term Clock
#45
#43, 44
#42
t
GRP
GRP
#22
gsu) - (
t
t
gh) - (
gco) + (
t
io +
t
io +
t
orp +
t
grp +
t
grp +
Reg 4 PT Bypass
#33, 34,
XOR Delays
Control
PTs
t
Feedback
#25, 26, 27
ob)
t
20 PT
35
ptck(min))
#24
t
20ptxor)
Comb 4 PT Bypass #23
9
OE
RE
CK
Specifications ispLSI 2096VE
GLB
GLB Reg Bypass
D
RST
Table 2-0042/2096VE
GLB Reg
Delay
#28
#29, 30,
31, 32
Q
ORP Bypass
Delay
ORP
ORP
#36
#37
#40, 41
0491/2032
#38,
39
I/O Cell
(Output)
I/O Pin