isplsi2096a-80ltn128i Lattice Semiconductor Corp., isplsi2096a-80ltn128i Datasheet - Page 7

• Manufacturer Part Number: isplsi2096a-80ltn128i
• Description: In-system Programmable High Density Pld
• Manufacturer: Lattice Semiconductor Corp.

Derivations of
Note: Calculations are based upon timing specifications for the ispLSI 2096/A-125L.
GOE 0,1
ispLSI 2096/A Timing Model
Ded. In
Y0,1,2
I/O Pin
Reset
(Input)
t
t
t
su
h
co
3.5 ns
2.6 ns
9.3 ns
=
=
=
=
=
=
=
=
=
=
=
=
I/O Delay
Logic + Reg su - Clock (min)
(
(#20+ #22+ #26) + (#29) - (#20+ #22+ #35)
(0.2 + 1.3 + 6.0) + (0.8) - (0.2 + 1.3 + 3.3)
Clock (max) + Reg h - Logic
(
(#20+ #22+ #35) + (#30) - (#20+ #22+ #26)
(0.2 + 1.3 + 5.6) + (3.0) - (0.2 + 1.3 + 6.0)
Clock (max) + Reg co + Output
(
(#20+ #22+ #35) + (#31) + (#36 + #38)
(0.2 + 1.3 + 5.6) + (0.2) + (0.8 + 1.2)
#21
#20
t
t
t
t
io +
io +
io +
I/O Cell
su,
t
t
t
t
grp +
grp +
grp +
h and
t
t
t
20ptxor) + (
ptck(max)) + (
ptck(max)) + (
t
co from the Product Term Clock
#45
#43, 44
#42
GRP
GRP
#22
t
gsu) - (
t
t
gh) - (
gco) + (
t
io +
t
io +
t
orp +
t
Reg 4 PT Bypass
grp +
t
grp +
#33, 34,
XOR Delays
Control
PTs
Feedback
#25, 26, 27
20 PT
35
t
#24
ob)
t
Comb 4 PT Bypass #23
ptck(min))
t
7
20ptxor)
OE
RE
CK
Specifications ispLSI 2096/A
Table 2-0042B/2096
GLB
GLB Reg Bypass
D
RST
GLB Reg
Delay
#28
#29, 30,
31, 32
Q
0491/2000
ORP Bypass
Delay
ORP
ORP
#36
#37
#40, 41
#38,
39
I/O Cell
(Output)
I/O Pin