gal22lv10z Lattice Semiconductor Corp., gal22lv10z Datasheet - Page 13

• Manufacturer Part Number: gal22lv10z
• Description: Low Voltage, Zero Power E2 Cmos Pld
• Manufacturer: Lattice Semiconductor Corp.

Circuitry within the GAL22LV10Z and GAL22LV10ZD provides
a reset signal to all registers during power-up. All internal registers
will have their Q outputs set low after a specified time (tpr, 10 s
MAX). As a result, the state on the registered output pins (if they
are enabled) will be either high or low on power-up, depending
on the programmed polarity of the output pins. This feature can
greatly simplify state machine design by providing a known state
on power-up. Because of the asynchronous nature of system
Power-Up Reset
Input/Output Equivalent Schematics
PIN
PIN
ESD
Protection
Circuit
ESD
Protection
Circuit
INTERNAL REGISTER
Typical Input
OUTPUT REGISTER
OUTPUT REGISTER
Vcc
ACTIVE HIGH
ACTIVE LOW
Q - OUTPUT
C L K
V c c
Vcc
Vcc (min.)
Vcc
13
t
pr
power-up, some conditions must be met to provide a valid power-
up reset of the device. First, the V
ond, the clock input must be at a static TTL level as shown in the
diagram during power up. The registers will reset within a maxi-
mum of tpr time. As in normal system operation, avoid clocking
the device until all input and feedback path setup times have been
met. The clock must also meet the minimum pulse width require-
ments.
Specifications GAL22LV10Z
Internal Register
Reset to Logic "0"
Device Pin
Reset to Logic "1"
Device Pin
Reset to Logic "0"
Data
Output
t
wl
t
su
Tri-State
Control
Feedback
Typical Output
Vcc
GAL22LV10ZD
Feedback
(To Input Buffer)
CC
rise must be monotonic. Sec-
PIN
PIN