hn58x2402sfpiage Renesas Electronics Corporation., hn58x2402sfpiage Datasheet - Page 11

• Manufacturer Part Number: hn58x2402sfpiage
• Description: Two-wire Serial Interface 2k Eeprom 256-word ?? 8-bit 4k Eeprom 512-word ?? 8-bit
• Manufacturer: Renesas Electronics Corporation.

HN58X2402SFPIAG/HN58X2404SFPIAG
Write Operations
Byte Write:
A write operation requires an 8-bit device address word with R/W = “0”. Then the EEPROM sends acknowledgment
"0" at the ninth clock cycle. After these, EEPROMs receive 8-bit memory address word. Upon receipt of this memory
address, the EEPROM outputs acknowledgment "0" and receives a following 8-bit write data. After receipt of write
data, the EEPROM outputs acknowledgment "0". If the EEPROM receives a stop condition, the EEPROM enters an
internally-timed write cycle and terminates receipt of SCL, SDA inputs until completion of the write cycle. The
EEPROM returns to a standby mode after completion of the write cycle.
Byte Write Operation
Page Write:
The EEPROM is capable of the page write operation which allows any number of bytes up to 8 bytes to be written in a
single write cycle. The page write is the same sequence as the byte write except for inputting the more write data. The
page write is initiated by a start condition, device address word, memory address(n) and write data(Dn) with every
ninth bit acknowledgment. The EEPROM enters the page write operation if the EEPROM receives more write
data(Dn+1) instead of receiving a stop condition. The a0 to a2 address bits are automatically incremented upon
receiving write data(Dn+1). The EEPROM can continue to receive write data up to 8 bytes. If the a0 to a2 address bits
reaches the last address of the page, the a0 to a2 address bits will roll over to the first address of the same page and
previous write data will be overwritten. Upon receiving a stop condition, the EEPROM stops receiving write data and
enters internally-timed write cycle.
Page Write Operation
Rev.4.00, Jul.13.2005, page 11 of 16
2k, 4k
Start
2k, 4k
1 0 1 0
Device
address
Start
1 0 1 0
Device
address
W
R/W
Memory
address (n)
ACK
W
R/W
Memory
address (n)
ACK
Write data (n)
ACK
ACK
Write data (n)
ACK
Write data (n+m)
ACK
Stop
ACK
Stop