hn58x2508fpiag Renesas Electronics Corporation., hn58x2508fpiag Datasheet
hn58x2508fpiag
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hn58x2508fpiag Summary of contents
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HN58X2508IAG Series HN58X2516IAG Series Serial Peripheral Interface 8k EEPROM (1024-word × 8-bit) 16k EEPROM (2048-word × 8-bit) Electrically Erasable and Programmable Read Only Memory Description HN58X25xxx Series is the Serial Peripheral Interface compatible (SPI) EEPROM (Electrically Erasable and Programmable ROM). ...
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... HN58X2508IAG Series, HN58X2516IAG Series Ordering Information Type No. Internal organization 8-kbit (1024 × 8-bit) HN58X2508FPIAG 16-kbit (2048 × 8-bit) HN58X2516FPIAG 8-kbit (1024 × 8-bit) HN58X2508TIAG 16-kbit (2048 × 8-bit) HN58X2516TIAG Pin Arrangement V Pin Description Pin name C Serial clock D Serial data input Q Serial data output ...
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HN58X2508IAG Series, HN58X2516IAG Series Block Diagram HOLD D Q Absolute Maximum Ratings Parameter Supply voltage relative Input voltage relative Operating temperature range* Storage temperature range Notes: ...
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HN58X2508IAG Series, HN58X2516IAG Series DC Characteristics Parameter Input leakage current Output leakage current V current Standby CC Active Output voltage Rev.1.00, Nov.08.2006, page Symbol Min Max ...
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HN58X2508IAG Series, HN58X2516IAG Series AC Characteristics Test Conditions • Input pules levels: V × 0 V × 0 • Input rise and fall time: ≤ • Input and ...
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HN58X2508IAG Series, HN58X2516IAG Series Parameter Clock frequency S active setup time S not active setup time S deselect time S active hold time S not active hold time Clock high time Clock low time Clock rise time Clock fall time ...
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HN58X2508IAG Series, HN58X2516IAG Series Timing Waveforms Serial Input Timing S t CHSL C t DVCH D High Impedance Q Hold Timing HOLD Output Timing S C ADDR D LSB IN t CLQV t CLQX Q Rev.1.00, ...
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HN58X2508IAG Series, HN58X2516IAG Series Pin Function Serial data output (Q) This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of serial clock (C). Serial data input (D) This ...
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HN58X2508IAG Series, HN58X2516IAG Series Functional Description Status Register The following figure shows the Status Register Format. The Status Register contains a number of status and control bits that can be read or set (as appropriate) by specific instructions. Status Register ...
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HN58X2508IAG Series, HN58X2516IAG Series Write Enable (WREN): The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction. The only way to do this is to send a Write Enable instruction to the device. As ...
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HN58X2508IAG Series, HN58X2516IAG Series Write Disable (WRDI): One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction to the device. As shown in the following figure, to send this instruction to the device, ...
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HN58X2508IAG Series, HN58X2516IAG Series Read Status Register (RDSR): The Read Status Register (RDSR) instruction allows the Status Register to be read. The Status Register may be read at any time, even while a Write or Write Status Register cycle is ...
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HN58X2508IAG Series, HN58X2516IAG Series Write Status Register (WRSR): The Write Status Register (WRSR) instruction allows new values to be written to the Status Register. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After ...
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HN58X2508IAG Series, HN58X2516IAG Series Read from Memory Array (READ): As shown in the following figure, to send this instruction to the device, chip select (S) is first driven low. The bits of the instruction byte and the address bytes are ...
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HN58X2508IAG Series, HN58X2516IAG Series Write to Memory Array (WRITE): As shown in the following figure, to send this instruction to the device, chip select (S) is first driven low. The bits of the instruction byte, address byte, and at least ...
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HN58X2508IAG Series, HN58X2516IAG Series Byte Write (WRITE) Sequence (Page ...
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HN58X2508IAG Series, HN58X2516IAG Series Data Protect The protection features of the device are summarized in the following table. When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial delivery state possible to ...
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HN58X2508IAG Series, HN58X2516IAG Series Hold Condition The hold (HOLD) signal is used to pause any serial communications with the device without resetting the clocking sequence. During the hold condition, the serial data output (Q) is high impedance, and serial data ...
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... HN58X2508IAG Series, HN58X2516IAG Series Package Dimensions HN58X2508FPIAG/HN58X2516FPIAG (PRSP0008DF-B / Previous Code: FP-8DBV) JEITA Package Code RENESAS Code P-SOP8-3.9x4.89-1.27 PRSP0008DF Index mark Rev.1.00, Nov.08.2006, page Previous Code MASS[Typ.] FP-8DBV 0.08g F 5 Terminal cross section ( Ni/Pd/Au plating ) NOTE) 1. DIMENSIONS" ...
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HN58X2508IAG Series, HN58X2516IAG Series HN58X2508TIAG/HN58X2516TIAG (PTSP0008JC-B / Previous Code: TTP-8DAV) JEITA Package Code RENESAS Code P-TSSOP8-4.4x3-0.65 PTSP0008JC Index mark Rev.1.00, Nov.08.2006, page Previous Code MASS[Typ.] TTP-8DAV 0.034g ...
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Revision History Rev. Date Page 1.00 Nov. 08, 2006 Initial issue HN58X2508IAG/HN58X2516IAG Series Data Sheet Contents of Modification Description ...
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Notes: 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained ...