hn58v256a Renesas Electronics Corporation., hn58v256a Datasheet

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hn58v256a

Manufacturer Part Number
hn58v256a
Description
Memory>eeprom>parallel Eeprom
Manufacturer
Renesas Electronics Corporation.
Datasheet
HN58V256A Series
HN58V257A Series
256k EEPROM (32-kword
Ready/Busy and RES function (HN58V257A)
Description
Renesas Technology
organized as 32768-word
by employing advanced MNOS memory technology and CMOS process and circuitry technology. They also
have a 64-byte page programming function to make their write operations faster.
Features
Rev.5.00, Nov. 17.2003, page 1 of 22
Single 3 V supply: 2.7 to 5.5 V
Access time: 120 ns max
Power dissipation:
On-chip latches: address, data, CE, OE, WE
Automatic byte write: 10 ms max
Automatic page write (64 bytes): 10 ms max
Ready/Busy (only the HN58V257A series)
Data polling and Toggle bit
Data protection circuit on power on/off
Conforms to JEDEC byte-wide standard
Reliable CMOS with MNOS cell technology
10
10 years data retention
Software data protection
Write protection by RES pin (only the HN58V257A series)
Industrial versions (Temperature range:
There are free also lead free products.
5
Active: 20 mW/MHz, (typ)
Standby: 110 W (max)
erase/write cycles (in page mode)
's
HN58V256A and HN58V257A are electrically erasable and programmable ROMs
8-bit. They have realized high speed, low power consumption and high reliability
20 to 85 C and 40 to 85 C) are also available.
8-bit)
(Previous ADE-203-357D (Z) Rev.4.0)
REJ03C0147-0500Z
Nov. 17. 2003
Rev. 5.00

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hn58v256a Summary of contents

Page 1

... Ready/Busy and RES function (HN58V257A) Description 's Renesas Technology HN58V256A and HN58V257A are electrically erasable and programmable ROMs organized as 32768-word 8-bit. They have realized high speed, low power consumption and high reliability by employing advanced MNOS memory technology and CMOS process and circuitry technology. They also have a 64-byte page programming function to make their write operations faster ...

Page 2

... HN58V256A Series, HN58V257A Series Ordering Information Type No. Access time HN58V256AFP-12 120 ns HN58V256AT-12 120 ns HN58V257AT-12 120 ns HN58V256AFP-12E 120 ns HN58V256AT-12E 120 ns HN58V257AT-12E 120 ns Pin Arrangement HN58V256AFP Series A14 A12 A13 A11 ...

Page 3

... HN58V256A Series, HN58V257A Series Pin Description Pin name A0 to A14 I/ RDY/Busy* RES Note: 1. This function is supported by only the HN58V257A series. Block Diagram Note: 1. This function is supported by only the HN58V257A series High voltage generator V SS RES ...

Page 4

... HN58V256A Series, HN58V257A Series Operation Table Operation Read Standby Write Deselect Write inhibit V IL Data polling Program reset Notes: 1. Refer to the recommended DC operating condition Don’t care 3. This function is supported by only the HN58V267A series. ...

Page 5

... HN58V256A Series, HN58V257A Series DC Characteristics ( + Parameter Symbol Min Input leakage current I LI Output leakage current I LO Standby V current I CC CC1 I CC2 Operating V current I CC CC3 Output low voltage V OL Output high voltage RES = 100 A max (only the HN58V257A series) Note: 1 ...

Page 6

... HN58V256A Series, HN58V257A Series AC Characteristics ( + Test Conditions Input pulse levels Input rise and fall time Input timing reference levels: 0.8, 1.8 V Output load: 1TTL Gate +100 pF Output reference levels: 1.5 V, 1.5 V Read Cycle Parameter Symbol Address to output delay ...

Page 7

... HN58V256A Series, HN58V257A Series Write Cycle Parameter Address setup time Address hold time CE to write setup time (WE controlled) CE hold time (WE controlled write setup time (CE controlled) WE hold time (CE controlled write setup time OE hold time Data setup time Data hold time ...

Page 8

... HN58V256A Series, HN58V257A Series Timing Waveforms Read Timing Waveform Address CE OE High WE Data Out RES 2 * Rev.5.00, Nov. 17.2003, page ACC Data out valid DFR ...

Page 9

... HN58V256A Series, HN58V257A Series Byte Write Timing Waveform (1) (WE Controlled) Address Din High-Z Busy 2 RDY RES RES Rev.5.00, Nov. 17.2003, page OES OEH t DW High-Z ...

Page 10

... HN58V256A Series, HN58V257A Series Byte Write Timing Waveform (2) (CE Controlled) Address Din High-Z Busy 2 RDY RES RES Rev.5.00, Nov. 17.2003, page OES t OEH High-Z ...

Page 11

... HN58V256A Series, HN58V257A Series Page Write Timing Waveform (1) (WE Controlled) *7 Address A0 to A14 OES Din t DB Busy High-Z 2 RDY RES RES V CC Rev.5.00, Nov. 17.2003, page BLC ...

Page 12

... HN58V256A Series, HN58V257A Series Page Write Timing Waveform (2) (CE Controlled) *8 Address A0 to A14 OES Din t DB Busy High-Z 2 RDY RES RES V CC Rev.5.00, Nov. 17.2003, page BLC ...

Page 13

... HN58V256A Series, HN58V257A Series Data Data Polling Timing Waveform Data Data Address OEH Din X I/O7 Rev.5.00, Nov. 17.2003, page Dout OES t DW Dout X ...

Page 14

... HN58V256A Series, HN58V257A Series Toggle bit This device provide another function to determine the internal programming cycle. If the EEPROM is set to read mode during the internal programming cycle, I/O6 will charge from “1” to “0” (toggling) for each read. When the internal programming cycle is finished, toggling of I/O6 will stop and the device can be accessible for next read or program ...

Page 15

... HN58V256A Series, HN58V257A Series Software Data Protection Timing Waveform (1) (in protection mode Address 5555 Data AA Software Data Protection Timing Waveform (2) (in non-protection mode Address 5555 2AAA Data AA 55 Rev.5.00, Nov. 17.2003, page BLC 5555 Write address 2AAA ...

Page 16

... HN58V256A Series, HN58V257A Series Functional Description Automatic Page Write Page-mode write feature allows bytes of data to be written into the EEPROM in a single write cycle. Following the initial byte cycle, an additional bytes can be written in the same manner. Each additional byte load cycle must be started within 30 µs from the preceding falling edge CE. When high for 100 µ ...

Page 17

... HN58V256A Series, HN58V257A Series WE WE Pin Operation During a write cycle, addresses are latched by the falling edge CE, and data is latched by the rising edge CE. Write/Erase Endurance and Data Retention Time 5 The endurance is 10 cycles in case of the page programming and 10 (1% cumulative failure rate) ...

Page 18

... HN58V256A Series, HN58V257A Series 2. Data Protection at V On/Off CC When V is turned on or off, noise on the control pins generated by external circuits (CPU, etc) may act trigger and turn the EEPROM to program mode by mistake. To prevent this unintentional programming, the EEPROM must be kept in an unprogrammable state while the CPU unstable state ...

Page 19

... HN58V256A Series, HN58V257A Series 3. Software data protection To prevent unintentional programming, this device has the software data protection (SDP) mode. The SDP is enabled by inputting the following 3 bytes code and write data. SDP is not enabled if only the 3 bytes code is input. To program data in the SDP enable mode, 3 bytes code must be input before write data ...

Page 20

... HN58V256A Series, HN58V257A Series Package Dimensions HN58V256AFP Series (FP-28D, FP-28DV) 18.3 18.8 Max 28 1 1.12 Max 1.27 *0.40 ± 0.08 0.38 ± 0.06 *Dimension including the plating thickness Base material dimension Rev.5.00, Nov. 17.2003, page 11.8 ± 0.3 1.0 ± 0.2 0.15 0.20 M Package Code JEDEC JEITA Mass (reference value) Unit: mm 1.7 0˚ – 8˚ ...

Page 21

... HN58V256A Series, HN58V257A Series Package Dimensions (cont.) HN58V256AT Series (TFP-28DB, TFP-28DBV) 8.00 8.20 Max 0.55 *0.22 ± 0.08 0.10 0.20 ± 0.06 0.45 Max 0.10 *Dimension including the plating thickness Base material dimension Rev.5.00, Nov. 17.2003, page 13.40 ± 0.30 0 ˚ – 5 ˚ Package Code JEDEC JEITA Mass (reference value) Unit ...

Page 22

... HN58V256A Series, HN58V257A Series Package Dimensions (cont.) HN58V257AT Series (TFP-32DA, TFP-32DAV) 8.00 8.20 Max 0.50 *0.22 ± 0.08 0.08 0.20 ± 0.06 0.45 Max 0.10 *Dimension including the plating thickness Base material dimension Rev.5.00, Nov. 17.2003, page 14.00 ± 0.20 Package Code JEDEC JEITA Mass (reference value) Unit: mm 0.80 0 ˚ – 5 ˚ ...

Page 23

... Recommended DC Operating Conditions Deletion of Device Group Deletion of Operating temperature range Deletion of note 4 Change order of notes 1.0 Apr. 12. 1995 Change of format 2 Operating Information Deletion of HN58V256A-15 and HN58V257A-15 Deletion of note 1 Deletion of Compatible type No. Deletion of Operating temperature range 3 Pin Description Addition of note 1 3 Block Diagram Addition of note 1 ...

Page 24

... May. 20. 1997 16 Functional Description Data protection 3: Change of Description 4.0 Oct. 24. 1997 8 Timing Waveforms Read Timing Waveform: Correct error 5.00 Nov. 17. 2003 Change format issued by Renesas Technology Corp. 2 Ordering Information Addition of HN58V256AFP-12E, HN58V256AT-12E, HN58V257AT-12E 20-22 Package Dimensions FP-28D to FP-28D, FP-28DV TFP-28DB to TFP-28DB, TFP-28DBV TFP-32DA to TFP-32DA, TFP-32DAV ...

Page 25

Sales Strategic Planning Div. Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble ...

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