am29lv008bb-90ek Meet Spansion Inc., am29lv008bb-90ek Datasheet - Page 10

• Manufacturer Part Number: am29lv008bb-90ek
• Description: 8 Mbit 1 M ? 8-bit
• Manufacturer: Meet Spansion Inc.

Characteristics” section contains timing specification
tables and timing diagrams for write operations.
Program and Erase Operation Status
During an erase or program operation, the system may
check the status of the operation by reading the status
bits on DQ7–DQ0. Standard read cycle timings and I
read specifications apply. Refer to “Write Operation
Status” for more information, and to “AC Characteris-
tics” for timing diagrams.
Standby Mode
When the system is not reading or writing to the device,
it can place the device in the standby mode. In this
mode, current consumption is greatly reduced, and the
outputs are placed in the high impedance state, inde-
pendent of the OE# input.
The device enters the CMOS standby mode when the
CE# and RESET# pins are both held at V
(Note that this is a more restricted voltage range than
V
V
the standby current will be greater. The device requires
standard access time (t
device is in either of these standby modes, before it is
ready to read data.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
In the DC Characteristics table, I
sents the standby current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device
energy consumption. The device automatically enables
this mode when addresses remain stable for t
ns. The automatic sleep mode is independent of the
CE#, WE#, and OE# control signals. Standard address
access timings provide new data when addresses are
changed. While in sleep mode, output data is latched
and always available to the system. I
10
IH
CC
.) If CE# and RESET# are held at V
± 0.3 V, the device will be in the standby mode, but
CE
) for read access when the
CC3
IH
and I
CC5
, but not within
CC
CC4
in the DC
ACC
± 0.3 V.
D A T A S H E E T
repre-
Am29LV008B
+ 30
CC
Characteristics table represents the automatic sleep
mode current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of reset-
ting the device to reading array data. When the
RESET# pin is driven low for at least a period of t
device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the internal state
machine to reading array data. The operation that was
interrupted should be reinitiated once the device is
ready to accept another command sequence, to
ensure data integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V
draws CMOS standby current (I
at V
be greater.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
If RESET# is asserted during a program or erase oper-
ation, the RY/BY# pin remains a “0” (busy) until the
internal reset operation is complete, which requires a
time of t
system can thus monitor RY/BY# to determine whether
the reset operation is complete. If RESET# is asserted
when a program or erase operation is not executing
(RY/BY# pin is “1”), the reset operation is completed
within a time of t
rithms). The system can read data t
RESET# pin returns to V
Refer to the AC Characteristics tables for RESET#
parameters and to Figure 14 for the timing diagram.
Output Disable Mode
When the OE# input is at V
disabled. The output pins are placed in the high imped-
ance state.
IL
but not within V
READY
(during Embedded Algorithms). The
READY
SS
±0.3 V, the standby current will
(not during Embedded Algo-
IH
21524D6 October 11, 2006
.
IH
, output from the device is
CC4
SS
). If RESET# is held
±0.3 V, the device
RH
after the
RP
, the