as7c33128ft18b ETC-unknow, as7c33128ft18b Datasheet
as7c33128ft18b
Related parts for as7c33128ft18b
as7c33128ft18b Summary of contents
Page 1
... D Q Enable Output register Buffers CE CLK D Q Enable Power delay down register CLK –65 -75 7.5 8.5 6.5 7.5 250 225 120 100 30 30 Alliance Semiconductor AS7C33128FT18B DDQ 128K × 18 Memory array Input registers CLK 18 DQ [a,b] -80 -10 Units 10 12 8.0 10.0 200 175 Copyright © ...
Page 2
... Pipelined Burst Synchronous SRAM - Single Cycle Deselect PL-DCD : Pipelined Burst Synchronous SRAM - Double Cycle Deselect FT : Flow-through Burst Synchronous SRAM 12/10/04; v.1.3 ® 1,2 Mode PL-SCD PL-SCD PL-SCD PL-DCD PL-DCD PL-DCD Alliance Semiconductor AS7C33128FT18B Speed 200/166/133 MHz 200/166/133 MHz 200/166/133 MHz 200/166/133 MHz 200/166/133 MHz 200/166/133 MHz 6.5/7.5/8.0/10 ns 6.5/7.5/8.0/10 ns 6.5/7.5/8.0/ ...
Page 3
... DQb5 DDQ V 21 SSQ DQb6 22 DQb7 23 DQpb SSQ V 27 DDQ 12/10/04; v.1.3 ® TQFP 14 × 20mm Alliance Semiconductor AS7C33128FT18B DDQ V 76 SSQ NC 75 DQpa 74 DQa7 73 DQa6 SSQ V 70 DDQ DQa5 69 DQa4 68 VSS ...
Page 4
... WE signals are sampled on the clock edge that samples ADSC low (and ADSP high). • Master chip enable CE0 blocks ADSP, but not ADSC. The AS7C33128FT18B family operates from a core 3.3V power supply. I/Os use a separate power supply that can operate at 2.5V or 3.3V. These devices are available in a 100-pin TQFP package. ...
Page 5
... DESELECT or READ cycle should be given while the SRAM is transitioning out of SNOOZE PUS MODE. 12/10/04; v.1.3 ® Description or left floating, device follows interleaved Burst order. When DD is guaranteed after the time t is met. After entering SNOOZE MODE, all inputs except ZZ ZZI Alliance Semiconductor AS7C33128FT18B . The duration of SB2 ...
Page 6
... Address Address Address Address Alliance Semiconductor AS7C33128FT18B ...
Page 7
... H H Current External Next Next Current Current Alliance Semiconductor AS7C33128FT18B CLK Operation Deselect Hi− Deselect Hi− Deselect Hi− Deselect Hi− Deselect Hi− Begin read Begin read Hi−Z ...
Page 8
... D I – OUT T –65 stg T –65 bias Symbol Min V 3.135 DD V 3.135 DDQ Vss 0 Symbol Min V 3.135 DD V 2.375 DDQ Vss 0 Alliance Semiconductor AS7C33128FT18B Max Unit +4 0 0.5 V DDQ 1 °C +150 °C +135 Nominal Max Unit 3.3 3.465 V 3.3 3.465 ...
Page 9
... Deselected < Max IL Deselected < 0.2V, ≤ 0.2V or ≥ V all V – 0. ≥ V Deselected – 0.2V, Max DD ≤ ≥ V all Alliance Semiconductor AS7C33128FT18B Min Max Unit -2 2 µA < µA DDQ +0.3 DDQ -0.3** 0.8 V -0.5** ...
Page 10
... ADSCS t 0.5 – 0.5 – ADVH t 0.5 – 0.5 – ADSPH t 0.5 – 0.5 – ADSCH Conditions Symbol ZZ > SB2 t PDS t PUS t ZZI t RZZI Alliance Semiconductor AS7C33128FT18B -80 –10 Notes Min Max Unit 10 – 12 – ns – 8.0 – – 4.0 – 4.0 ns 2.5 – 2.5 – ns 2,3,4 2.5 – 2.5 – – ...
Page 11
... ADV inserts wait states t HZOE t OH Q(A2Ý01) Q(A2Ý10) Q(A2Ý11 Read Burst Burst Suspend Burst Q(A2) Read Read Read Read Q(A 2Ý01 ) Q(A 2Ý10 ) Q(A 2Ý10 ) Q(A 2Ý11 ) Alliance Semiconductor AS7C33128FT18B Undefined A3 Q(A3Ý11) Q(A3) Q(A3Ý01) Q(A3Ý10) t HZC Read Burst Burst Burst Q(A3) Read Read Read DSEL Q(A 3Ý01 ) Q(A 3Ý10 ) Q(A 3Ý ...
Page 12
... ADSC LOADS NEW ADDRESS A2 ADV SUSPENDS BURST D(A2) D(A2Ý01) D(A2Ý01) D(A2Ý10) Read Suspend ADV Suspend ADV Q(A2) Write Burst Write Burst D D(A 2Ý01 ) Write Write D(A 2Ý01 ) D(A 2Ý10 ) Alliance Semiconductor AS7C33128FT18B t ADSCS t ADSCH ADVS t ADVH D(A2Ý11) D(A3) D(A3Ý01) D(A3Ý10) ADV ADV ...
Page 13
... ADVS t ADVH D(A2 HZOE LZOE Q(A1) Suspend Read Suspend Read Read Q(A2) Write Q(A3) Q(A1) D Alliance Semiconductor AS7C33128FT18B t OH Q(A3) Q(A3Ý01) Q(A3Ý10) Q(A3Ý11) ADV ADV ADV Suspend Burst Burst Burst Read Read Read Read Q(A 3Ý11 ) Q(A 3Ý01 ) Q(A 3Ý10 ) Q(A 3Ý ...
Page 14
... Din READ READ Q(A1) Q(A2) Note: ADV is don’t care here. 12/10/04; v.1.3 ® t CYC HZOE Q(A3) Q(A4 D(A5) D(A6) D(A7) READ WRITE READ WRITE Q(A3) D(A6) Q(A4) D(A5) Alliance Semiconductor AS7C33128FT18B A10 Q(A9) Q(A10) D(A8) READ WRITE WRITE READ Q(A10) D(A7) D(A8) Q(A9 ...
Page 15
... OE t LZOE Din t HZC Dout Q(A1) t PDS ZZ ZZ Setup Cycle t ZZI I supply READ READ Q(A1) Q(A1Ý01) 12/10/04; v.1.3 ® PUS ZZ Recovery Cycle t RZZI I SB2 Sleep State Alliance Semiconductor AS7C33128FT18B t CYC HZOE Q(A2) Q(A2(Ý01)) Normal Operation Mode READ READ Q(A2) Q(A2Ý01 ...
Page 16
... L for 3.3V I/ DDQ for 2.5V I/O Figure B: Output load (A) at any given temperature and voltage. LZC Alliance Semiconductor AS7C33128FT18B Thevenin equivalent: +3.3V for 3.3V I/O; /+2.5V for 2.5V I/O 319Ω / 1667Ω D OUT 5 pF* 353Ω / 1538Ω GND *including scope and jig capacitanc Figure C: Output load (B) ...
Page 17
... Package Dimensions 100-pin quad flat pack (TQFP TQFP Min Max A1 0.05 0.15 A2 1.35 1.45 b 0.22 0.38 c 0.09 0.20 D 13.90 14.10 E 19.90 20.10 e 0.65 nominal Hd 15.85 16.15 He 21.80 22.20 L 0.45 0.75 L1 1.00 nominal α 0° 7° Dimensions in millimeters 12/10/04; v.1.3 ® Alliance Semiconductor AS7C33128FT18B α ...
Page 18
... Operating temperature: C=Commercial ( 0° 70° C); I=Industrial ( -40 ° 85° Lead free part 12/10/04; v.1.3 ® -75 AS7C33128FT18B- AS7C33128FT18B- 75TQC 80TQC AS7C33128FT18B- AS7C33128FT18B- 75TQI 80TQI – Alliance Semiconductor AS7C33128FT18B –80 –10 AS7C33128FT18B- 10TQC AS7C33128FT18B- 10TQI AS7C33128FT18B-65TQCN ...
Page 19
... Alliance products in such life- supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use. AS7C33128FT18B ® Copyright © Alliance Semiconductor All Rights Reserved Part Number: AS7C33128FT18B Document Version: v.1.3 ...