as7c251mntf3236a ETC-unknow, as7c251mntf3236a Datasheet
as7c251mntf3236a
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as7c251mntf3236a Summary of contents
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December 2004 2.5V 1M × 32/36 Flowthrough SRAM with NTD Features • Organization: 1,048,576 words × bits ™ • NTD architecture for efficient bus operation • Fast clock to data access: 7.5/8.5/10 ns • Fast OE access ...
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Mb Synchronous SRAM products list Org Part Number 2MX18 AS7C252MPFS18A 1MX32 AS7C251MPFS32A 1MX36 AS7C251MPFS36A 2MX18 AS7C252MPFD18A 1MX32 AS7C251MPFD32A 1MX36 AS7C251MPFD36A 2MX18 AS7C252MFT18A 1MX32 AS7C251MFT32A 1MX36 AS7C251MFT36A 2MX18 AS7C252MNTD18A 1MX32 AS7C251MNTD32A 1MX36 AS7C251MNTD36A 2MX18 AS7C252MNTF18A 1MX32 AS7C251MNTF32A 1MX36 AS7C251MNTF36A ...
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Pin diagram 100-pin TQFP - top view NC/DQPc 1 DQc0 2 DQc1 DDQ V 5 SSQ DQc2 6 DQc3 7 DQc4 8 DQc5 SSQ V 11 DDQ 12 DQc6 DQc7 ...
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Functional Description The AS7C251MNTF32A/36A family is a high performance CMOS 32 Mbit synchronous Static Random Access Memory (SRAM) organized as 1,048,576 words × bits and incorporates a LATE Write. This variation of the 32Mb+ synchronous SRAM uses ...
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Signal descriptions Signal I/O Properties CLK I CLOCK Clock. All inputs except OE, LBO, and ZZ are synchronous to this clock. CEN I SYNC Clock enable. When de-asserted high, the clock input signal is masked SYNC ...
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Burst order Interleaved burst order LBO = Starting address First increment Second increment Third increment [5,6,7,8,9,11] Synchronous truth table ...
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State diagram for NTD SRAM Read Write Absolute maximum ratings Parameter Power supply voltage relative to GND Input voltage relative to GND (input pins) Input voltage relative to GND (I/O pins) Power dissipation Short circuit output current Storage temperature Temperature ...
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DC electrical characteristics Parameter Sym † Input leakage current |I Output leakage current |I Input high (logic 1) voltage V Input low (logic 0) voltage V Output high voltage V Output low voltage V † LBO and ZZ pins have ...
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Timing characteristics over operating range Parameter Cycle time Clock access time Output enable low to data valid Clock high to output low Z Data Output invalid from clock high Output enable low to output low Z Output enable high to ...
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Key to switching waveforms Rising input Timing waveform of read cycle CLK t t CENS CENH CEN Address R CSS CSH CE0,CE2 CE1 t t ADVS ADVH ADV/LD OE ...
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Timing waveform of write cycle CLK t t CENS CENH CEN Address R/W BWn t t CSS CSH CE0,CE2 CE1 t t ADVS ADVH ADV/LD OE D(A1) Din t HZOE Dout Q(n-1) WRITE DSEL Command ...
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Timing waveform of read/write cycle CLK t t CENS CENH CEN ADDRESS R BWn t t CSH CSS CE0, CE2 CE1 t t ADVH ADVS ADV/LD ...
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NOP, stall and deselect cycles CLK CEN CE1 CE0, CE2 ADV/LD R/W BWn Address A1 D/Q Q(A1) READ BURST Command Q(A1) Q(A1 Ý Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low. OE ...
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Timing waveform of snooze mode CLK ZZ setup cycle ZZ t ZZI I supply I SB2 All inputs Deselect or Read Only (except ZZ) Dout 12/23/04, v 1.1 ® t PUS ZZ recovery cycle t RZZI Deselect or Read Only ...
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AC test conditions • Output load: For LZC LZOE HZOE • Input pulse level: GND to 3V. See Figure A. • Input rise and fall time (measured at 0.3V and 2.7V): 2 ns. See Figure ...
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Package dimensions 100-pin quad flat pack (TQFP) TQFP Min Max A1 0.05 0.15 A2 1.35 1.45 b 0.22 0.38 c 0.09 0.20 D 13.90 14.10 E 19.90 20.10 e 0.65 nominal Hd 15.85 16.15 He 21.80 22.20 L 0.45 0.75 ...
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Ordering information Package & –75 Width AS7C251MNTF32A-75TQC TQFP x32 AS7C251MNTF32A-75TQI AS7C251MNTF36A-75TQC TQFP x36 AS7C251MNTF36A-75TQI Notes: Add suffix ‘N’ to the above part number for Lead Free Parts (Ex. AS7C251MNTF32A-75TQCN) Part numbering guide AS7C Alliance ...
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Alliance Semiconductor Corporation 2575, Augustine Drive, Santa Clara, CA 95054 Tel: 408 - 855 - 4900 Fax: 408 - 855 - 4999 www.alsc.com © Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt ...