as7c251mntd3236a ETC-unknow, as7c251mntd3236a Datasheet
as7c251mntd3236a
Manufacturer Part Number
as7c251mntd3236a
Description
Manufacturer
ETC-unknow
Datasheet
1.AS7C251MNTD3236A.pdf
(18 pages)
Logic block diagram
Selection guide
Features
• Organization: 1,048,576 words × 32 or 36 bits
• NTD
• Fast clock speeds to 200 MHz
• Fast clock to data access: 3.2/3.5/3.8 ns
• Fast OE access time: 3.2/3.5/3.8 ns
• Fully synchronous operation
• pipelined mode
• Common data inputs and data outputs
• Asynchronous output enable control
January 2005
Minimum cycle time
Maximum clock frequency
Maximum clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
1/17/05, V 1.2
™
architecture for efficient bus operation
A[19:0]
CE1
CE2
CE0
DQ[a,b,c,d]
ADV / LD
BWa
BWb
BWc
BWd
LBO
2.5V 1M × 32/36 Pipelined SRAM with NTD
R/W
ZZ
CLK
CEN
32/36
20
D
D
Control
Burst logic
Address
Register
register
logic
CLK
Input
Data
CLK
Alliance Semiconductor
CLK
Q
Q
-200
200
450
170
3.2
90
5
• Available in 100-pin TQFP packages
• Byte write enables
• Clock enable for operation hold
• Multiple chip enables for easy expansion
• 2.5V core power supply
• Self-timed write cycles
• Interleaved or linear burst modes
• Snooze mode for standby operation
20
OE
32/36
D
addr. registers
CLK
Write delay
®
-166
166
400
150
3.5
90
6
32/36
Q
OE
CLK
32/36
CLK
Output
Register
32/36
1M x 32/36
DQ[a,b,c,d]
20
TM
SRAM
32/36
Array
AS7C251MNTD32A
AS7C251MNTD36A
Copyright © Alliance Semiconductor. All rights reserved.
-133
133
350
140
7.5
3.8
90
P. 1 of 18
Units
MHz
mA
mA
mA
ns
ns
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