as7c251mft3236a ETC-unknow, as7c251mft3236a Datasheet
as7c251mft3236a
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as7c251mft3236a Summary of contents
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January 2005 2.5V 1M × 32/36 Flow-through synchronous SRAM Features • Organization: 1,048,576 words × bits • Fast clock to data access: 7.5/8.5/10 ns • Fast OE access time: 3.5/4.0 ns • Fully synchronous flow-through operation • ...
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Mb Synchronous SRAM products list Org Part Number 2MX18 AS7C252MPFS18A 1MX32 AS7C251MPFS32A 1MX36 AS7C251MPFS36A 2MX18 AS7C252MPFD18A 1MX32 AS7C251MPFD32A 1MX36 AS7C251MPFD36A 2MX18 AS7C252MFT18A 1MX32 AS7C251MFT32A 1MX36 AS7C251MFT36A 2MX18 AS7C252MNTD18A 1MX32 AS7C251MNTD32A 1MX36 AS7C251MNTD36A 2MX18 AS7C252MNTF18A 1MX32 AS7C251MNTF32A 1MX36 AS7C251MNTF36A ...
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Pin assignment 100-pin TQFP - top view NC/DQPc 1 DQc0 2 DQc1 DDQ V 5 SSQ 6 DQc2 DQc3 7 DQc4 8 DQc5 SSQ V 11 DDQ 12 DQc6 DQc7 ...
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Functional description The AS7C251MFT32A/36A is a high-performance CMOS 32-Mbit synchronous Static Random Access Memory (SRAM) device organized as 1,048,576 words × bits. Fast cycle times of 8.5/10/12 ns with clock access times (t Burst operation is initiated ...
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Signal descriptions Pin I/O Properties CLK I CLOCK Clock. All inputs except OE, ZZ, and LBO are synchronous to this clock. A,A0,A1 I SYNC Address. Sampled when all chip enables are active and when ADSC or ADSP are asserted. DQ[a,b,c,d] ...
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Write enable truth table (per byte) Function GWE BWE L Write All Bytes H H Write Byte a H Write Byte c and d H Read H Key don’t care low high ...
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Synchronous truth table 1 CE0 CE1 CE2 ADSP ADSC ...
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Absolute maximum ratings Parameter Power supply voltage relative to GND Input voltage relative to GND (input pins) Input voltage relative to GND (I/O pins) Power dissipation Short circuit output current Storage temperature Temperature under bias Stresses greater than those listed ...
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DC electrical characteristics Parameter Sym † Input leakage current |I Output leakage current |I Input high (logic 1) voltage V Input low (logic 0) voltage V Output high voltage V Output low voltage V † LBO and ZZ pins have ...
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Timing characteristics over operating range Parameter Cycle time Clock access time Output enable low to data valid Clock high to output low Z Data output invalid from clock high Output enable low to output low Z Output enable high to ...
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Key to switching waveforms Rising input Timing waveform of read cycle CLK t t ADSPS ADSPH ADSP t ADSCS ADSC Address GWE, BWE t t CSS CSH CE0, CE2 CE1 ...
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Timing waveform of write cycle t CH CLK t ADSPS t ADSPH ADSP ADSC Address BWE BW[a:d] t CSS t CSH CE0, CE2 CE1 ADV OE Din D(A1) Read Suspend Q(A1) Note: Ý = XOR ...
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Timing waveform of read/write cycle (ADSP Controlled; ADSC High) CLK t ADSPS t ADSPH ADSP Address A1 BWE BW[a:d] CE0, CE2 CE1 ADV OE Din LZC Dout Q(A1) Read Q(A1) Note: Ý = XOR when LBO = ...
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Timing waveform of read/write cycle(ADSC controlled, ADSP = HIGH) CLK t t ADSCS ADSCH ADSC ADDRESS BWE BW[a: CSS CSH CE0,CE2 CE1 LZOE Q(A1) Q(A2) Dout Din READ READ Q(A1) Q(A2) ...
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Timing waveform of power down cycle CLK t t ADSPS ADSPS ADSP ADSC A1 ADDRESS BWE BW[a: CSS CSH CE0,CE2 CE1 ADV LZOE Din Dout Q(A1) t PDS ZZ ZZ Setup Cycle t ZZI ...
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AC test conditions • Output load: For LZC LZOE HZOE • Input pulse level: GND to 2.5V. See Figure A. • Input rise and fall time (measured at 0.25V and 2.25V): 2 ns. See Figure ...
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Package dimensions 100-pin quad flat pack (TQFP) TQFP Min Max A1 0.05 0.15 A2 1.35 1.45 b 0.22 0.38 c 0.09 0.20 D 13.90 14.10 E 19.90 20.10 e 0.65 nominal Hd 15.85 16.15 He 21.80 22.20 L 0.45 0.75 ...
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Ordering information Package & Width AS7C251MFT32A-75TQC TQFP x32 AS7C251MFT32A-75TQI AS7C251MFT36A-75TQC TQFP x36 AS7C251MFT36A-75TQI Note: Add suffix ‘N’ to the above part number for Lead Free Parts (Ex. AS7C251MFT32A-85TQCN) Part numbering guide AS7C 1.Alliance Semiconductor SRAM ...
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