as7c25512ntf3236a ETC-unknow, as7c25512ntf3236a Datasheet
as7c25512ntf3236a
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as7c25512ntf3236a Summary of contents
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April 2005 2.5V 512K × 32/36 Flowthrough Synchronous SRAM with NTD Features • Organization: 524,288 words × bits ™ • NTD architecture for efficient bus operation • Fast clock to data access: 7.5/8.5/10 ns • Fast OE ...
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... AS7C25512NTF32A 512KX36 AS7C25512NTF36A 1 Core Power Supply: VDD = 2.5V + 0.125V 2 I/O Supply Voltage: VDDQ = 2.5V + 0.125V 3 Refer corresponding product datasheets for the latest information on Clock Speed and Clock Access Time availability. PL-SCD : Pipelined Burst Synchronous SRAM - Single Cycle Deselect PL-DCD : Pipelined Burst Synchronous SRAM - Double Cycle Deselect ...
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TQFP - top view NC/DQPc 1 2 DQc0 DQc1 DDQ V 5 SSQ 6 DQc2 DQc3 7 DQc4 8 DQc5 SSQ V 11 DDQ 12 DQc6 DQc7 ...
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Functional Description The AS7C25512NTF32A/36A family is a high performance CMOS 16 Mbit synchronous Static Random Access Memory (SRAM) organized as 524,288 words × bits and incorporates a LATE Write. This variation of the 16Mb+ synchronous SRAM uses ...
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Signal descriptions Signal I/O Properties CLK I CLOCK Clock. All inputs except OE, LBO, and ZZ are synchronous to this clock. CEN I SYNC Clock enable. When de-asserted high, the clock input signal is masked SYNC ...
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Burst order Interleaved burst order (LBO = Starting address First increment Second increment Third increment [5,6,7,8,9,11] Synchronous truth table ...
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State diagram for NTD SRAM Read Write Absolute maximum ratings Parameter Power supply voltage relative to GND Input voltage relative to GND (input pins) Input voltage relative to GND (I/O pins) Power dissipation Short circuit output current Storage temperature Temperature ...
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DC electrical characteristics Parameter Sym † Input leakage current |I Output leakage current |I Input high (logic 1) voltage V Input low (logic 0) voltage V Output high voltage V Output low voltage V † LBO and ZZ pins have ...
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Timing characteristics over operating range Parameter Cycle time Clock access time Output enable low to data valid Clock high to output low Z Data Output invalid from clock high Output enable low to output low Z Output enable high to ...
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Key to switching waveforms Rising input Timing waveform of read cycle CLK t t CES CEH CEN Address R BWn t CSH CE0,CE2 CE1 t t ADVS ...
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Timing waveform of write cycle CLK t t CES CEH CEN Address R/W BWn t CSH CE0,CE2 CE1 t t ADVS ADVH ADV/LD OE Din t HZOE Dout Q(n-2) Q(n-1) Write DSEL D(A1) 4/21/05, v ...
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Timing waveform of read/write cycle CLK t t CENS CENH CEN CE1 t t CSS CSH CE0, CE2 t t ADVS ADVH ADV/ R BWn ADDRESS A1 A2 ...
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NOP, stall and deselect cycles CLK CEN CE1 CE0, CE2 ADV/LD R/W BWn Address A1 D/Q Command Read Burst Q(A1) Q(A1Ý01) Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low low. ...
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Timing waveform of snooze mode CLK ZZ setup cycle ZZ t ZZI I supply I SB2 All inputs Deselect or Read Only (except ZZ) Dout 4/21/05, v 1.2 ® t PUS ZZ recovery cycle t RZZI Deselect or Read Only ...
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AC test conditions • Output load: For LZC LZOE HZOE • Input pulse level: GND to 2.5V. See Figure A. • Input rise and fall time (measured at 0.25V and 2.25V): 1.0V/ns. See Figure A. ...
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Package dimensions 100-pin quad flat pack (TQFP) TQFP Min Max A1 0.05 0.15 A2 1.35 1.45 b 0.22 0.38 c 0.09 0.20 D 13.90 14.10 E 19.90 20.10 e 0.65 nominal Hd 15.85 16.15 He 21.80 22.20 L 0.45 0.75 ...
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Ordering information Package & Width AS7C25512NTF32A-75TQC TQFP x32 AS7C25512NTF32A-75TQI AS7C25512NTF36A-75TQC TQFP x36 AS7C25512NTF36A-75TQI Notes: Add suffix ‘N’ to the above part number for Lead Free Parts (Ex. AS7C25512NTF32A-85TQCN) Part numbering guide AS7C 25 512 Alliance Semiconductor ...
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