as7c25512pfd3236a ETC-unknow, as7c25512pfd3236a Datasheet
as7c25512pfd3236a
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as7c25512pfd3236a Summary of contents
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February 2005 2.5V 512K × 32/36 pipelined burst synchronous SRAM Features • Organization: 524,288 words × bits • Fast clock speeds to 166 MHz • Fast clock to data access: 3.5/3.8 ns • Fast OE access time: ...
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Mb 2.5V Synchronous SRAM products list Org Part Number 1MX18 AS7C251MPFS18A 512KX32 AS7C25512PFS32A 512KX36 AS7C25512PFS36A 1MX18 AS7C251MPFD18A 512KX32 AS7C25512PFD32A 512KX36 AS7C25512PFD36A 1MX18 AS7C251MFT18A 512KX32 AS7C25512FT32A 512KX36 AS7C25512FT36A 1MX18 AS7C251MNTD18A 512KX32 AS7C25512NTD32A 512KX36 AS7C25512NTD36A 1MX18 AS7C251MNTF18A 512KX32 AS7C25512NTF32A 512KX36 AS7C25512NTF36A ...
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Pin assignment 100-pin TQFP - top view NC/DQPc 1 DQc0 2 DQc1 DDQ V 5 SSQ 6 DQc2 DQc3 7 8 DQc4 DQc5 SSQ V 11 DDQ 12 DQc6 DQc7 ...
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Functional description The AS7C25512PFD32A/36A is a high-performance CMOS 16-Mbit synchronous Static Random Access Memory (SRAM) device organized as 524,288 words x 32/36. It incorporates a two-stage register-register pipeline for highest frequency on any given technology. Fast cycle times of 6/7.5 ...
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Signal descriptions Pin I/O Properties Description CLK I CLOCK Clock. All inputs except OE, ZZ, and LBO are synchronous to this clock. A,A0,A1 I SYNC Address. Sampled when all chip enables are active and when ADSC or ADSP are asserted. ...
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Write enable truth table (per byte) Function GWE BWE L Write All Bytes H Write Byte a H Write Byte c and Read H Key don’t care low high ...
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Synchronous truth table 1 CE0 CE1 CE2 ADSP ADSC ...
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Absolute maximum ratings Parameter Power supply voltage relative to GND Input voltage relative to GND (input pins) Input voltage relative to GND (I/O pins) Power dissipation Short circuit output current Storage temperature Temperature under bias Stresses greater than those listed ...
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DC electrical characteristics Parameter Sym † Input leakage current |I Output leakage current |I Input high (logic 1) voltage V Input low (logic 0) voltage V Output high voltage V Output low voltage V † LBO and ZZ pins have ...
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Timing characteristics over operating range Parameter Clock frequency Cycle time Clock access time Output enable low to data valid Clock high to output low Z Data output invalid from clock high Output enable low to output low Z Output enable ...
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Key to switching waveforms Rising input Timing waveform of read cycle CLK t ADSPS t ADSPH ADSP t ADSCS ADSC Address GWE, BWE t t CSS CSH CE0, CE2 CE1 ...
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Timing waveform of write cycle t CH CLK t t ADSPS ADSPH ADSP ADSC Address BWE BW[a: CSS CSH CE0, CE2 CE1 ADV OE Din D(A1) Read Sus- Q(A1) pend Write D(A1) Note: ...
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Timing waveform of read/write cycle (ADSP Controlled; ADSC High) CLK t t ADSPS ADSPH ADSP Address A1 GWE CE0, CE2 CE1 ADV OE Din Dout DSEL Read Q(A1) Note: Ý = XOR when LBO = high/no connect; Ý = ADD ...
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Timing waveform of read/write cycle(ADSC controlled, ADSP = HIGH) CLK t t ADSCS ADSCH ADSC ADDRESS GWE t t CSS CSH CE0,CE2 CE1 ADV LZOE Q(A1) Dout Din READ READ Q(A1) Q(A2) 2/10/05, ...
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Timing waveform of power down cycle CLK t t ADSPS ADSPS ADSP ADSC A1 ADDRESS GWE t t CSS CSH CE0,CE2 CE1 ADV LZOE Din Dout Q(A1 supply S READ USPEND READ Q(A1) Q(A1) ...
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AC test conditions • Output load: For LZC LZOE HZOE • Input pulse level: GND to 2.5V. See Figure A. • Input rise and fall time (measured at 0.25V and 2.25V): 2 ns. See Figure ...
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Package dimensions 100-pin quad flat pack (TQFP) TQFP Min Max A1 0.05 0.15 A2 1.35 1.45 b 0.22 0.38 c 0.09 0.20 D 13.90 14.10 E 19.90 20.10 e 0.65 nominal Hd 15.85 16.15 He 21.80 22.20 L 0.45 0.75 ...
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Ordering information Package & Width TQFP x32 TQFP x36 Note: Add suffix ‘N’ to the above part numbers for Lead Free Parts (Ex. AS7C25512PFD32A-166TQCN) Part numbering guide AS7C 25 512 Alliance Semiconductor SRAM prefix 2. Operating ...
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