gs8160e32bt-250v GSI Technology, gs8160e32bt-250v Datasheet

gs8160e32bt-250v

Manufacturer Part Number

gs8160e32bt-250v

Description

1m X 18, 512k X 32, 512k X 36 18mb Sync Burst Srams

Manufacturer

GSI Technology

Datasheet

1.GS8160E32BT-250V.pdf (23 pages)

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100-Pin TQFP

Commercial Temp

Industrial Temp

Features

• FT pin for user-configurable flow through or pipeline

• Dual Cycle Deselect (DCD) operation

• 1.8 V or 2.5 V core power supply

• 1.8 V or 2.5 V I/O supply

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Default to Interleaved Pipeline mode

• Byte Write (BW) and/or Global Write (GW) operation

• Internal self-timed write cycle

• Automatic power-down for portable applications

• JEDEC-standard 100-lead TQFP package

• RoHS-compliant 100-lead TQFP package available

Functional Description

Applications

The GS8160ExxBT-xxxV is an 18,874,368-bit (16,777,216-bit

for x32 version) high performance synchronous SRAM with a

2-bit burst address counter. Although of a type originally

developed for Level 2 Cache applications supporting high

performance CPUs, the device now finds application in

synchronous SRAM applications, ranging from DSP main

store to networking chip set support.

Controls

Addresses, data I/Os, chip enables (E1, E2, E3), address burst

control inputs (ADSP, ADSC, ADV), and write control inputs

(Bx, BW, GW) are synchronous and are controlled by a

positive-edge-triggered clock input (CK). Output enable (G)

and power down control (ZZ) are asynchronous inputs. Burst

cycles can be initiated with either ADSP or ADSC inputs. In

Burst mode, subsequent burst addresses are generated

internally and are controlled by ADV. The burst address

counter may be configured to count in either linear or

Rev: 1.01 5/2006

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

operation

Flow Through

Pipeline

3-1-1-1

2-1-1-1

1M x 18, 512K x 32, 512K x 36

18Mb Sync Burst SRAMs

Curr

tCycle

Parameter Synopsis

(x32/x36)

(x18)

1/23

interleave order with the Linear Burst Order (LBO) input. The

Burst function need not be used. New addresses can be loaded

on every cycle with no degradation of chip performance.

Flow Through/Pipeline Reads

The function of the Data Output register can be controlled by

the user via the FT mode pin (Pin 14). Holding the FT mode

pin low places the RAM in Flow Through mode, causing

output data to bypass the Data Output Register. Holding FT

high places the RAM in Pipeline mode, activating the rising-

edge-triggered Data Output Register.

DCD Pipelined Reads

The GS8160ExxBT-xxxV is a DCD (Dual Cycle Deselect)

pipelined synchronous SRAM. SCD (Single Cycle Deselect)

versions are also available. DCD SRAMs pipeline disable

commands to the same degree as read commands. DCD RAMs

hold the deselect command for one full cycle and then begin

turning off their outputs just after the second rising edge of

clock.

Byte Write and Global Write

Byte write operation is performed by using Byte Write enable

(BW) input combined with one or more individual byte write

signals (Bx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the Byte Write

control inputs.

Sleep Mode

Low power (Sleep mode) is attained through the assertion

(High) of the ZZ signal, or by stopping the clock (CK).

Memory data is retained during Sleep mode.

Core and Interface Voltages

The GS8160ExxBT-xxxV operates on a 1.8 V or 2.5 V power

supply. All input are 1.8 V or 2.5 V compatible. Separate

output power (V

from the internal circuits and are 1.8 V or 2.5 V compatible.

-250

280

330

210

240

3.0

4.0

5.5

-200

230

270

185

205

3.0

5.0

6.5

DDQ

-150

185

210

170

190

3.8

6.7

7.5

) pins are used to decouple output noise

Unit

GS8160ExxBT-xxxV

250 MHz–150 MHz

1.8 V or 2.5 V V

1.8 V or 2.5 V I/O

Preliminary

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gs8160e32bt-250v Summary of contents

Page 1

... KQ 5.5 tCycle 210 Curr (x18) 240 Curr (x32/x36) 1/23 Preliminary GS8160ExxBT-xxxV 250 MHz–150 MHz 2.5 V I/O ) pins are used to decouple output noise DDQ -150 Unit 3.0 3.8 ns 5.0 6.7 ns 230 185 mA 270 210 mA 6.5 7.5 ns 6.5 7.5 ns 185 170 mA 205 190 mA © 2004, GSI Technology DD ...

Page 2

Page 3

... Rev: 1.01 5/2006 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8160E32BT-xxxV 100-Pin TQFP Pinout 512K x 32 Top View 3/23 Preliminary GS8160ExxBT-xxxV ...

Page 4

Page 5

... Burst address counter advance enable; active low Address Strobe (Processor, Cache Controller); active low Sleep Mode control; active high Flow Through or Pipeline mode; active low Linear Burst Order mode; active low Core power supply I/O and Core Ground Output driver power supply 5/23 Preliminary GS8160ExxBT-xxxV © 2004, GSI Technology ...

Page 6

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8160ExxBT-xxxV Block Diagram Counter Load Register D Q Register D Q Register D Q Register D Q Register D Q Register D Q Register 6/23 Preliminary GS8160ExxBT-xxxV A Memory Array DQx1–DQx9 © 2004, GSI Technology ...

Page 7

... Note: The burst counter wraps to initial state on the 5th clock. 7/23 Preliminary GS8160ExxBT-xxxV Function Linear Burst Interleaved Burst Flow Through Pipeline Active Standby A[1:0] A[1:0] A[1:0] A[1: BPR 1999.05.18 © 2004, GSI Technology ...

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Page 9

Page 10

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Simplified State Diagram X Deselect First Write Burst Write CR CW 10/23 Preliminary GS8160ExxBT-xxxV First Read Burst Read BW, and GW © 2004, GSI Technology ...

Page 11

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Simplified State Diagram with G X Deselect First Write Burst Write 11/23 Preliminary GS8160ExxBT-xxxV First Read Burst Read CR © 2004, GSI Technology ...

Page 12

... V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. DDn 12/23 Preliminary GS8160ExxBT-xxxV Value –0.5 to 4.6 –0 –0 +0.5 (≤ 4.6 V max.) DDQ –0 +0.5 (≤ 4.6 V max.) DD +/–20 +/–20 1.5 –55 to 125 –55 to 125 Typ. Max. Unit 1.8 2.0 V 2 © 2004, GSI Technology Unit Notes ...

Page 13

... V V Symbol Test conditions I/O OUT 13/23 Preliminary GS8160ExxBT-xxxV Typ. Max. Unit V + 0.3 V — DD 0.3*V V — DD Typ. Max. Unit ° ° 20% tKC DD IL Typ. Max. Unit © 2004, GSI Technology Notes 1 1 Notes 2 2 ...

Page 14

... Figure 1 Output Load 1 * 50Ω 30pF V DDQ/2 * Distributed Test Jig Capacitance Min – ≥ –100 –1 uA OUT DD Min = 1 – 0.4 V DDQ DDQ = 2.375 V 1.7 V — — © 2004, GSI Technology Max 1 uA 100 Max — — 0.4 V 0.4 V ...

Page 15

... GSI Technology Unit ...

Page 16

... GSI Technology ...

Page 17

... Pipeline Mode Timing (DCD) Deselect Deselect Write B Read C Read C+1 Read C+2 Read C+3 Cont tKL tKL tKH tKH tKC tKC ADSC initiated read and E3 only sampled with ADSC tS tKQ tOHZ tH tLZ Q(A) D(B) 17/23 Preliminary GS8160ExxBT-xxxV Deselect Deselect Deselected with E1 tHZ Q(C) Q(C+1) Q(C+2) Q(C+3) © 2004, GSI Technology tKQX ...

Page 18

... Flow Through Mode Timing (DCD) Deselect Write B Read C Read C+1 Read C+2 Read C+3 Read C tKL tKL tKC tKC Fixed High tS tH ADSC initiated read masks ADSP E1 masks ADSP tH tS tOHZ tLZ Q(A) D(B) Q(C) 18/23 Preliminary GS8160ExxBT-xxxV Deselect tH Deselected with E1 tKQX tHZ Q(C+1) Q(C+2) Q(C+3) Q(C) © 2004, GSI Technology ...

Page 19

... Rev: 1.01 5/2006 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Sleep Mode Timing tKH tKH tKC tKC tKL tKL tZZS tZZH 19/23 Preliminary GS8160ExxBT-xxxV 2. The duration of SB tZZR © 2004, GSI Technology ...

Page 20

... All dimensions are in millimeters (mm). 2. Package width and length do not include mold protrusion. Rev: 1.01 5/2006 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. θ 0.10 0.15 1.40 1.45 0.30 0.40 — 0.20 e 22.0 22.1 20.0 20.1 16.0 16.1 b 14.0 14.1 0.65 — 0.60 0.75 1.00 — 0.10 — 7° 20/23 Preliminary GS8160ExxBT-xxxV E1 E © 2004, GSI Technology ...

Page 21

... Ordering Information for GSI Synchronous Burst RAMs 1 Org Part Number GS8160E18BT-250V GS8160E18BT-200V GS8160E18BT-150V 512K x 32 GS8160E32BT-250V 512K x 32 GS8160E32BT-200V 512K x 32 GS8160E32BT-150V 512K x 36 GS8160E36BT-250V 512K x 36 GS8160E36BT-200V 512K x 36 GS8160E36BT-150V GS8160E18BT-250IV GS8160E18BT-200IV GS8160E18BT-150IV 512K x 32 ...

Page 22

... GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings. Rev: 1.01 5/2006 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. ...

Page 23

... New Format or Content GS8160EVxxB_r1 GS8160EVxxB_r1; GS8160ExxB-xxxV_r_01 Rev: 1.01 5/2006 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. • Creation of new datasheet • Changed part numbering due to change in product Content nomenclature 23/23 Preliminary GS8160ExxBT-xxxV Page;Revisions;Reason © 2004, GSI Technology ...

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