gs840e32agt-180i GSI Technology, gs840e32agt-180i Datasheet - Page 11

• Manufacturer Part Number: gs840e32agt-180i
• Description: 256k X 18, 128k X 32, 128k X 36 4mb Sync Burst Srams
• Manufacturer: GSI Technology

Mode Pin Functions
Note:
There are pull-up devices on LBO and FT pins and a pull down device on the ZZ pin, so those input pins can be unconnected and the chip will
operate in the default states as specified in the above tables.
Burst Counter Sequences
Linear Burst Sequence
Note:
The burst counter wraps to initial state on the 5th clock.
Rev: 1.14 10/2007
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
1st address
2nd address
3rd address
4th address
Output Register Control
Power Down Control
Burst Order Control
Mode Name
A[1:0] A[1:0] A[1:0] A[1:0]
00
01
10
11
01
10
00
11
Name
10
11
00
01
LBO
Pin
ZZ
FT
00
01
10
11
H or NC
H or NC
L or NC
State
H
L
L
11/32
Standby, I
Interleaved Burst Sequence
Note:
The burst counter wraps to initial state on the 5th clock.
Interleaved Burst
1st address
2nd address
3rd address
4th address
Flow Through
Linear Burst
Function
Pipeline
Active
DD
= I
GS840E18/32/36AT/B-180/166/150/100
SB
A[1:0] A[1:0] A[1:0] A[1:0]
00
01
10
11
01
00
11
10
10
00
01
11
© 1999, GSI Technology
11
10
01
00