gs840fh32at-8i GSI Technology, gs840fh32at-8i Datasheet

gs840fh32at-8i

Manufacturer Part Number

gs840fh32at-8i

Description

256k X 18, 128k X 32, 128k X 36 4mb Sync Burst Srams

Manufacturer

GSI Technology

Datasheet

1.GS840FH32AT-8I.pdf (22 pages)

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TQFP

Commercial Temp

Industrial Temp

Features

• Flow Through mode operation

• 3.3 V +10%/–5% core power supply

• 2.5 V or 3.3 V I/O supply

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Default to Interleaved Pipeline mode

• Byte Write (BW) and/or Global Write (GW) operation

• Common data inputs and data outputs

• Clock Control, registered, address, data, and control

• Internal self-timed write cycle

• Automatic power-down for portable applications

• JEDEC-standard 100-lead TQFP

• RoHS-compliant 100-lead TQFP package available

Functional Description

Applications

The GS840FH18/32/36A is a 4,718,592-bit (4,194,304-bit for

x32 version) high performance synchronous SRAM with a

2-bit burst address counter. Although of a type originally

developed for Level 2 Cache applications supporting high

performance CPUs, the device now finds application in

synchronous SRAM applications ranging from DSP main store

to networking chip set support. The GS840FH18/32/36A is

available in a JEDEC-standard 100-lead TQFP package.

Controls

Addresses, data I/Os, chip enables (E

control inputs (ADSP, ADSC, ADV), and write control inputs

(Bx, BW, GW) are synchronous and are controlled by a

positive-edge-triggered clock input (CK). Output enable (G)

and power down control (ZZ) are asynchronous inputs. Burst

cycles can be initiated with either ADSP or ADSC inputs. In

Burst mode, subsequent burst addresses are generated

internally and are controlled by ADV. The burst address

Rev: 1.08 4/2007

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

, E

Through

2-1-1-1

Flow

256K x 18, 128K x 32, 128K x 36

, E

), address burst

4Mb Sync Burst SRAMs

tCycle

Parameter Synopsis

1/22

210 mA

8 ns

9 ns

-8

190 mA

8.5 ns

10 ns

counter may be configured to count in either linear or

interleave order with the Linear Burst Order (LBO) input. The

burst function need not be used. New addresses can be loaded

on every cycle with no degradation of chip performance.

Designing For Compatibility

The JEDEC standard for Burst RAMs calls for a FT mode pin

option (Pin 14 on TQFP). Board sites for flow through Burst

RAMs should be designed with V

location to ensure the broadest access to multiple vendor

sources. Boards designed with FT pin pads tied low may be

stuffed with GSI’s pipeline/flow through-configurable Burst

RAMs or any vendor’s flow through or configurable Burst

SRAM. Bumps designed with the FT pin location tied high or

floating must employ a non-configurable flow through Burst

RAM, (e.g., GS840FH18/32/36A), to achieve flow through

functionality.

Byte Write and Global Write

Byte write operation is performed by using Byte Write enable

(BW) input combined with one or more individual byte write

signals (Bx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the byte write

control inputs.

Sleep Mode

Low power (Sleep mode) is attained through the assertion

(High) of the ZZ signal, or by stopping the clock (CK).

Memory data is retained during Sleep mode.

Core and Interface Voltages

The GS840FH18/32/36A operates on a 3.3 V power supply

and all inputs/outputs are 3.3 V- and 2.5 V-compatible.

Separate output power (V

output noise from the internal circuit.

-8.5

165 mA

10 ns

12 ns

-10

135 mA

12 ns

15 ns

-12

GS840FH18/32/36AT-8/8.5/10/12

DDQ

) pins are used to decouple

connected to the FT pin

3.3 V and 2.5 V I/O

8 ns–12 ns

3.3 V V

Related parts for gs840fh32at-8i

gs840fh32at-8i Summary of contents

Page 1

... Parameter Synopsis -8 -8.5 -10 Flow 8 Through tCycle 2-1-1-1 I 210 mA 190 mA 165 mA DD 1/22 GS840FH18/32/36AT-8/8.5/10/12 8 ns– 3.3 V and 2.5 V I/O connected to the FT pin SS ) pins are used to decouple DDQ - 135 mA © 1999, GSI Technology DD ...

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... Data I/O Pin; Byte A 9th Data I/O Pin; Byte B 9th Data I/O Pin; Byte C 9th Data I/O Pin; Byte D Sleep Mode control; active high Linear Burst Order mode; active low Core power supply I/O and Core Ground Output driver power supply No Connect 5/22 © 1999, GSI Technology ...

Page 6

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS840FH18/32/36A Block Diagram Counter Load Register D Q Register D Q Register D Q Register D Q Register D Q Register D Q Register 6/22 GS840FH18/32/36AT-8/8.5/10/12 A Memory Array DQxn–DQxn © 1999, GSI Technology ...

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... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Simplified State Diagram X Deselect First Write Burst Write 9/22 GS840FH18/32/36AT-8/8.5/10/ First Read Burst Read and Write ( BW, and GW) control © 1999, GSI Technology ...

Page 10

... Data Input Set Up Time. Rev: 1.08 4/2007 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. X Deselect First Write Burst Write 10/22 GS840FH18/32/36AT-8/8.5/10/ First Read Burst Read CR © 1999, GSI Technology ...

Page 11

... V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. DDn 11/22 GS840FH18/32/36AT-8/8.5/10/12 Value –0.5 to 4.6 –0.5 to 4.6 –0 +0.5 (≤ 4.6 V max.) DDQ –0 +0.5 (≤ 4.6 V max.) DD +/–20 +/–20 1.5 –55 to 125 –55 to 125 Typ. Max. Unit 3.3 3.6 V 3.3 3.6 V 2.5 2.7 V © 1999, GSI Technology Unit Notes ...

Page 12

... V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. DDn Overshoot Measurement and Timing 12/22 Max. Unit Notes 0.3 V 1,3 DDQ 0 0.3 V 1,3 DDQ 0.3*V V 1,3 DD Max. Unit Notes ° ° 50% tKC © 1999, GSI Technology ...

Page 13

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Symbol Test conditions I/O OUT Conditions V – DDQ Fig. 1 Output Load 1 DQ 50Ω V DDQ/2 * Distributed Test Jig Capacitance 13/22 GS840FH18/32/36AT-8/8.5/10/12 Typ. Max. Unit 30pF © 1999, GSI Technology ...

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... GSI Technology Unit Unit ...

Page 16

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Flow Through Mode Timing Cont Write B Read C Read C+1 Read C+2 Read C+3 Read C tKL tKL tKC tKC Fixed High tS tH ADSC initiated read tKQ tOHZ tLZ D(B) Q(C) 16/22 GS840FH18/32/36AT-8/8.5/10/12 Cont Deselect Deselected with E1 tHZ Q(C+1) Q(C+2) Q(C+3) Q(C) © 1999, GSI Technology tKQX ...

Page 17

... CK Setup Hold ADSP ADSC ZZ Rev: 1.08 4/2007 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Sleep Mode Timing Diagram tKH tKH tKC tKC tKL tKL tZZS tZZH 17/22 GS840FH18/32/36AT-8/8.5/10/12 tZZR © 1999, GSI Technology ...

Page 18

... PD HD Rev: 1.08 4/2007 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. 0 Out (Pull Down) VDDQ - V Out (Pull Up 18/22 GS840FH18/32/36AT-8/8.5/10/12 VDDQ I Out VOut VSS 2.5 3 3 © 1999, GSI Technology ...

Page 19

... All dimensions are in millimeters (mm). 2. Package width and length do not include mold protrusion. Rev: 1.08 4/2007 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. θ 0.10 0.15 1.40 1.45 0.30 0.40 — 0.20 e 22.0 22.1 20.0 20.1 16.0 16.1 b 14.0 14.1 0.65 — 0.60 0.75 1.00 — 0.10 7 ° — 19/22 GS840FH18/32/36AT-8/8.5/10/ © 1999, GSI Technology ...

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... GS840FH36AT-10 128K x 36 GS840FH36AT-12 256K x 18 GS840FH18AT-8I 256K x 18 GS840FH18AT-8.5I 256K x 18 GS840FH18AT-10I 256K x 18 GS840FH18AT-12I 128K x 32 GS840FH32AT-8I 128K x 32 GS840FH32AT-8.5I 128K x 32 GS840FH32AT-10I 128K x 32 GS840FH32AT-12I 128K x 36 GS840FH36AT-8I 128K x 36 GS840FH36AT-8.5I 128K x 36 GS840FH36AT-10I 128K x 36 ...

Page 21

... GS840FH36AGT-12I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS840FH32AT-7.5T. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipelined mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user ...

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... Content • Changed Pb-free to RoHS-compliant (entire document) • Updated Power Supply Voltage Ranges table (pg. 11) Content • Updated Logic Level tables (pg. 12) • Added note to TQFP pinout (pg 22/22 GS840FH18/32/36AT-8/8.5/10/ table on page 1 and Operating © 1999, GSI Technology ...

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