vrs51c1100 ETC-unknow, vrs51c1100 Datasheet - Page 19

• Manufacturer Part Number: vrs51c1100
• Description: Versa 8051 Mcu With 128kb Of Iap/isp Flash
• Manufacturer: ETC-unknow

Timer 0, Timer 1 Counter / Timer Functions
Timing Function
When Timer 1 or Timer 0 is configured to operate as a
timer, its value is automatically incremented at every
machine cycle. Once the timer value rolls over, a flag
is raised and the counter acquires a value of zero. The
overflow flags (TF0 and TF1) are located in the TCON
register.
The TR0 and TR1 bits of the TCON register gate the
corresponding timer operation. In order for the timer to
run, the corresponding TRx bit must be set to 1.
The IT0 and IT1 bits of the TCON register control the
event that will trigger an external interrupt as follows:
IT0 = 0: The INT0, if enabled, occurs if a low level is
IT0 = 1: The INT0, if enabled, occurs if a high to low
IT1 = 0: The INT1, if enabled, occurs if a low level is
IT1 = 1: The INT1, if enabled, occurs if a high to low
The IE0 and IE1 bits of the TCON register are external
flags that indicate whether a transition has been
detected on the INT0 and INT1 interrupt pins,
respectively.
If the external interrupt is configured as edge sensitive,
the corresponding IE0 and IE1 flags are automatically
cleared when the corresponding interrupt is serviced.
If the external interrupt is configured as level sensitive,
the corresponding flag must be cleared by the
software.
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VRS51C1100
present on P3.2
transition is detected on P3.2
present on P3.3
transition is detected on P3.3
T
Counting Function
When operating as a counter, the timer’s register is
incremented at every falling edge of the T0 and T1
signals located at the input of the timer.
When the sampling circuit sees a high immediately
followed by a low in the next machine cycle, the
counter is incremented. Two machine cycles are
required to detect and record an event. In order to be
properly sampled, the duration of the event presented
to the timer input should be greater than 1/24 of the
oscillator frequency.
Timer 0 / Timer 1 Operating Modes
The user may change the operating mode by setting
the M1 and M0 bits of the TMOD SFR.
ABLE
5
4
3
2
1
0
Bit
7
6
TF1
7
26: T
TF0
TR0
IE1
IT1
IE0
IT0
IMER
Mnemonic
TF1
TR1
TR1
6
0
AND
1 C
TF0
ONTROL
5
Description
Timer 1 Overflow Flag. Set by hardware on
Timer/Counter overflow. Cleared by
hardware on Timer/Counter overflow.
Cleared by hardware when processor
vectors to interrupt routine.
Timer 1 Run Control Bit. Set/cleared by
software to turn Timer/Counter on or off.
Timer 0 Overflow Flag. Set by hardware on
Timer/Counter overflow. Cleared by
hardware when processor vectors to
interrupt routine.
Timer 0 Run Control Bit. Set/cleared by
software to turn Timer/Counter on or off.
Interrupt Edge Flag. Set by hardware when
external interrupt edge is detected. Cleared
when interrupt processed.
Interrupt 1 Type Control Bit. Set/cleared by
software to specify falling edge/low level
triggered external interrupts.
Interrupt 0 Edge Flag. Set by hardware
when external interrupt edge is detected.
Cleared when interrupt processed.
Interrupt 0 Type control bit. Set/cleared by
software to specify falling edge/low level
triggered external interrupts.
R
EGISTER
TR0
4
(TCON) –SFR 88
IE1
3
IT1
2
H
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IE0
1
IT0
0