gs9005a Gennum Corporation, gs9005a Datasheet - Page 12

• Manufacturer Part Number: gs9005a
• Description: Serial Digital Receiver Corporation
• Manufacturer: Gennum Corporation

INPUT
10
520 - 28 - 11
All resistors in ohms, all capacitor
in microfarads, all inductors in
henries unless otherwise stated.
Application Note - PCB Layout
Special attention must be paid to component layout when designing high performance serial digital receivers. For background
information on high speed circuit and layout design concepts, refer to Document No. 521-32-00, “Optimizing Circuit and Layout
Design of the GS90005A/15A”. A recommended PCB layout can be found in the Gennum Application Note “EB9010B
Deserializer Evaluation Board.”
The use of a star grounding technique is required for the loop filter components of the GS9005A/15A.
Controlled impedance PCB traces should be used for the differential clock and data interconnection between the GS9005A and
the GS9000B or GS9000S. These differential traces must not pass over any ground plane discontinuities. A slot antenna is formed
when a microstrip trace runs across a break in the ground plane.
The series resistors at the parallel data output of the GS9000B or GS9000S are used to slow down the fast rise/fall time of the
GS9000B or GS9000S outputs. These resistors should be placed as close as possible to the GS9000B or GS9000S output pins
to minimize radiation from these pins.
GND
V
+5V
(1) Typical value for input return loss matching
(2) To reduce board space, the two anti-series 6.8 F capacitors (connected across pins 2 and 3
(3) Remove this potentiometer if P/N function is not required, and ground pin 16 of the GS9010A.
(4) The GS9000B will operate to a maximum frequency of 370 Mbps. The GS9000S will operate to
CC
Gennum Corporation assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement.
75
22n
REVISION NOTES
Changes to Figures 16, 17 and 20.
+
75
a maximum frequency of 300 Mbps.
of the GS9010A) may be replaced with a
(a) the 0.68 F capacitor connected to the OSC pin (11) of the GS9010A is replaced with a
(b) the GS9005A /15A Loop Filter Capacitor is 10nF.
(1)
0.33 F capacitor and
10
47p
DGND
113
DV
47p
+5V
CC
+
0.1
V
CC
V
CC
STAR
ROUTED
5.6p
ECL
DATA
INPUT
10
11
+
5
6
7
8
9
10
10n
DDI
DDI
VCC2
SDI
SDI
ƒ/2
VEE3
0.1
0.1
(2)
12 13 14 15 16 17 18
910
4
V
CC
6.8
6.8
GS9005A
0.1
3
0.1
(2)
1.2k
+
+
2
1
SSI
28 27 26
SWF
1.2k
120
V
Fig. 20 Typical Application Circuit
CC
SDO
SDO
SCO
SCO
SS1
SS0
CD
3.3n
V
CC
0.1
25
24
23
22
21
20
19
0.1 F
1
2
3
4
5
6
7
8
1.0 F non-polarized capacitor provided that:
V
0.1
CC
P/N
OUT
IN-
COMP
LF
ƒ/2
V CC
SWF
GS9010A
V
CC
HSYNC
FVCAP
STDT
GND
V CC
OSC
DLY
CD
100
16
15
14
13
12
11
10
9
390
390
100
100
390
390
100
V
CC
0.1
50k
V
CC
(3)
V
CC
180n
82n
10
11
12
5
6
7
8
9
DGND
DGND
DV
0.1
DV
SDI
SDI
SCI
SCI
SS1
SS0
SST
SWF
CC
CC
V
CC
100
© Copyright March 1991 Gennum Corporation. All rights reserved. Printed in Canada.
12 13 14 15 16
100k
68k
0.68
4
or GS9000S
GS9000B
3
(2)
DGND
3.3k
DGND
2
22n
1
100 100
(4)
100
28 27 26
17
100
PD7
PD6
PD5
PD4
PD3
PD2
PD1
18
DGND
0.1
DOCUMENT IDENTIFICATION
PRODUCT PROPOSAL
This data has been compiled for market investigation purposes
only, and does not constitute an offer for sale.
ADVANCE INFORMATION NOTE
This product is in development phase and specifications are
subject to change without notice. Gennum reserves the right to
remove the product at any time. Listing the product does not
constitute an offer for sale.
PRELIMINARY
The product is in a preproduction phase and specifications are
subject to change without notice.
DATA SHEET
The product is in production. Gennum reserves the right to
make changes at any time to improve reliability, function or
design, in order to provide the best product possible.
DGND
25
24
23
22
21
20
19
DV
CC
100
100
100
100
100
100
100
STANDARD TRUTH TABLE
ƒ/2
0
0
1
1
P/N
0
1
0
1
STANDARD
4:2:2 - 270
4:2:2 - 360
4ƒsc - NTSC
4ƒsc - PAL
INPUT SELECTION
SYNC WARNING FLAG
HSYNC OUTPUT
PARALLEL DATA BIT 9
PARALLEL DATA BIT 8
PARALLEL DATA BIT 7
PARALLEL DATA BIT 6
PARALLEL DATA BIT 5
PARALLEL DATA BIT 4
PARALLEL DATA BIT 3
PARALLEL DATA BIT 2
PARALLEL DATA BIT 1
PARALLEL DATA BIT 0
PARALLEL CLOCK OUT
SYNC CORRECTION ENABLE