pc1600cl Infineon Technologies Corporation, pc1600cl Datasheet - Page 20

• Manufacturer Part Number: pc1600cl
• Description: Registered Ddr Sdram-modules
• Manufacturer: Infineon Technologies Corporation

8) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge.
9) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but
10) Fast slew rate 1.0 V/ns , slow slew rate 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns,
11)
12) For each of the terms, if not already an integer, round to the next highest integer.
13) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
Data Sheet
A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes
were previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in
progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on
system performance (bus turnaround) degrades accordingly.
measured between
t
cycle time.
RPRES
is defined for CL = 1.5 operation only
V
OH(ac)
and
V
OL(ac)
.
20
HYS72D[128/64/32]5[00/20/21]GR–[7F/7/8]-B
Registered DDR SDRAM-Modules
t
CK
is equal to the actual system clock
Electrical Characteristics
t
Rev. 1.03 2004-01
DQSS
.