sic417 Vishay, sic417 Datasheet - Page 14

• Manufacturer Part Number: sic417
• Description: 10-a, 28-v Integrated Buck Regulator With Programmable Ldo
• Manufacturer: Vishay

SiC417
Vishay Siliconix
If the load release is relatively slow, the output capacitance
can be reduced. At heavy loads during normal switching,
when the FB pin is above the 500 mV reference, the DL
output is high and the low-side MOSFET is on. During this
time, the voltage across the inductor is approximately - V
This causes a down-slope or falling di/dt in the inductor. If the
load dI/dt is not much faster than the - dI/dt in the inductor,
then the inductor current will tend to track the falling load
current. This will reduce the excess inductive energy that
must be absorbed by the output capacitor, therefore a
smaller capacitance can be used.
The following can be used to calculate the needed
capacitance for a given dI
Peak inductor current is shown by the next equation.
I
I
Rate of change of load current = dI
I
Example
This would cause the output current to move from 10 A to
zero in 4 µs as shown by the following equation.
Note that C
compared to 595 µF based on a worst-case load release. To
meet the two design criteria of minimum 379 µF and
maximum 9 mΩ ESR, select two capacitors rated at 220 µF
and 15 mΩ ESR.
It is recommended that an additional small capacitor be
placed in parallel with C
switching noise.
Stability Considerations
Unstable operation is possible with adaptive on-time
controllers, and usually takes the form of double-pulsing or
ESR loop instability.
Double-pulsing occurs due to switching noise seen at the FB
input or because the FB ripple voltage is too low. This causes
the FB comparator to trigger prematurely after the 250 ns
minimum off-time has expired. In extreme cases the noise
can
Double-pulsing will result in higher ripple voltage at the
output, but in most applications it will not affect operation.
This form of instability can usually be avoided by providing
the FB pin with a smooth, clean ripple signal that is at least
10 mV
the output capacitors. It is also imperative to provide a proper
PCB layout as discussed in the Layout Guidelines section.
www.vishay.com
14
LPK
LPK
MAX
= I
= 10 + 1/2 x 4.4 = 12.2 A
= maximum load release = 10 A
p-p
cause
MAX
, which may dictate the need to increase the ESR of
C
C
OUT
OUT
+ 1/2 x I
OUT
C
OUT
= 12.2 x
= 379 µF
three
is much smaller in this example, 379 µF
= I
RIPPLEMAX
Load
LPK
0.88 µH x
or
OUT
x
LOAD
dl
L x
LOAD
dt
more
in order to filter high frequency
2 (1.15 - 1.05)
V
I
2 (V
LPK
OUT
/dt:
12.2
1.05
=
PK
2.5 A
-
LOAD
µs
- V
dl
I
successive
MAX
-
LOAD
OUT
2.5
10
/dt
)
x dt
x 1 µs
on-times.
New Product
OUT
.
Another way to eliminate doubling-pulsing is to add a small
(~ 10 pF) capacitor across the upper feedback resistor, as
shown in figure 13. This capacitor should be left unpopulated
until it can be confirmed that double-pulsing exists. Adding
the C
eliminate the problem. An optional connection on the PCB
should be available for this capacitor.
ESR loop instability is caused by insufficient ESR. The
details of this stability issue are discussed in the ESR
Requirements section. The best method for checking
stability is to apply a zero-to-full load transient and observe
the output voltage ripple envelope for overshoot and ringing.
Ringing for more than one cycle after the initial step is an
indication that the ESR should be increased.
One simple way to solve this problem is to add trace
resistance in the high current output path. A side effect of
adding trace resistance is output decreased load regulation.
ESR Requirements
A minimum ESR is required for two reasons. One reason is
to generate enough output ripple voltage to provide10 mV
at the FB pin (after the resistor divider) to avoid double-
pulsing.
The second reason is to prevent instability due to insufficient
ESR. The on-time control regulates the valley of the output
ripple voltage. This ripple voltage is the sum of the two
voltages. One is the ripple generated by the ESR, the other
is the ripple due to capacitive charging and discharging
during the switching cycle. For most applications the
minimum ESR ripple voltage is dominated by the output
capacitors, typically SP or POSCAP devices. For stability the
ESR zero of the output capacitor should be lower than
approximately one-third the switching frequency. The
formula for minimum ESR is shown by the following
equation.
For applications using ceramic output capacitors, the ESR is
normally too small to meet the above ESR criteria. In these
applications it is necessary to add a small virtual ESR
network composed of two capacitors and one resistor, as
shown in figure 14. This network creates a ramp voltage
V
OUT
TOP
capacitor will couple more ripple into FB to help
Figure 13 - Capacitor Coupling to FB Pin
ESR
MIN
C
=
TOP
R
2 x π x C
1
R
2
S09-0799-Rev. B, 11-May-09
3
OUT
Document Number: 69062
x f
To FB pin
SW
p-p