uc1602i-pp-m ETC-unknow, uc1602i-pp-m Datasheet - Page 15

• Manufacturer Part Number: uc1602i-pp-m
• Description: Single-chip, Ultra-low Power Passive Matrix Lcd Controller-driver
• Manufacturer: ETC-unknow

H
UC1602I series supports several parallel and
serial host interface formats.
System designers can use either the 8-bit parallel
bus to achieve the high data transfer rate, or use
serial bus to create LCD modules with as few as
9-pin connectors.
P
It is possible to interface UC1602I controllers
directly to either an 8080-style MPU bus or a
6800-style MCU bus with the following
connection.
Rev. 0.54 10/12/2001
ARALLEL
Address
Column
OST
Holder
D[7:0]
Write
Read
___
WR
Bus
CD
__
RD
Table 6: MPU bus control signal interface
Bus Type
Parallel
Serial
Bus
8080
6800
I
Table 5: Host interfaces Choices
NTERFACE
I
NTERFACE
L
LSB
2-wire (I
4-wire (S8)
Bus Type
L
8080
6800
D
WR0
R/W
L
___
WR
___
2
D
_ _
C)
Figure 5: Parallel Interface & Related Internal Signals
L
L+K
D
L+K
Access
D
L+K
R/W
R/W
R/W
WR1
L+K+1
W
___
RD
E
__
C
MSB
C
LSB
Dummy
The timing relationship between UC1602I internal
control signal RD, WR and their associated bus
actions are shown in the figure below. The
generation of UC1602I internal bus control
signals WR and RD is shown in the table below.
D
UC1602I Display Data RAM (RAM) read interface
is implemented as a two-stage pipe-line. This
architecture requires that, every time memory
address is modified, either in parallel mode or
serial mode, all three commands ( Set CA-LSB,
Set CA-MSB, Set PA ) need to be issued, and a
dummy read cycle need to be performed before
the actual data can propagate through the pipe-
line and be read from data port D[7:0].
There is no pipeline in write interface of RAM,
and the data is transferred directly from data bus
buffer to RAM.
C
ISPLAY
Bus Type
Dummy
8080
6800
Table 7: WR and RD signal generation
RAM D
D
C+1
C
D
C
!(WR1 & !WR0)
ATA
65x102 Matrix LCD Controller-Drivers
D
WR0
T
C+2
___
WR
C+1
RANSFER
D
___
C+1
C+3
M
!(WR1 & WR0)
MSB
UC1602I
WR1
___
RD
__
M
LSB
13
M