adf7011 Analog Devices, Inc., adf7011 Datasheet - Page 15

• Manufacturer Part Number: adf7011
• Description: High Performance Ism Band Ask/fsk/gfsk Transmitter Ic
• Manufacturer: Analog Devices, Inc.

CIRCUIT DESCRIPTION
Reference Input Section
The on-board crystal oscillator circuitry (Figure 2), allows the
use of an inexpensive quartz crystal as the PLL reference. The
oscillator circuit is enabled by setting XOE low. It is enabled by
default on power-up and is disabled by bringing CE low. Two
parallel resonant capacitors are required for oscillation at the
correct frequency; the value of these is dependant on the crystal
specification. Errors in the crystal can be corrected using the
error correction register within the R register. A single-ended
reference (TCXO, CXO) may be used. The CMOS levels should
be applied to OSC2, with XOE set high.
CLK
The CLK
oscillator section above and supplies a divided down 50:50 mark-
space signal to the CLK
available. This divide is set by the four MSBs in the R register.
On power-up, the CLK
The output buffer to CLK
the function register high. On power-up, this bit is set high.
The output buffer can drive up to a 20 pF load with a 10% rise
time at 4.8 MHz. Faster edges can result in some spurious
feedthrough to the output. A small series resistor (50 Ω) can be
used to slow the clock edges to reduce these spurs at F
R Counter
The 4-bit R Counter divides the reference input frequency by
an integer from 1 to 15. The divided down signal is presented
as the reference clock to the phase frequency detector (PFD).
The divide ratio is set in the R register. Maximizing the PFD
frequency reduces the N value. Having a higher PFD will
result in a higher level of spurious components. A PFD of
close to 4 MHz is recommended. This reduces the noise multi-
plied at a rate of 20 log(N) to the output, as well as reduces
occurrences of spurious components. The R register defaults
to R = 1 on power-up.
REV. 0
10pF
10pF
OSC1
OUT
Figure 2. Oscillator Circuit on the ADF7011
Divider and Buffer
OSC2
OSC1
OUT
DIVIDER
1 TO 15
circuit takes the reference clock signal from the
500k
Figure 3. CLK
OUT
XTAL OSCILLATOR
OUT
DIVIDE
100k
BY 2
OUT
DISABLED
defaults to divide by 16.
pin. An even divide from 2 to 30 is
is enabled by setting Bit DB4 in
OUT
SW1
DV
NC
DD
Stage
ENABLE BIT
100k
CLK
CLK
TO R COUNTER AND
OUT
OUT
CLK
BUFFER
CLK
OUT
.
DIVIDE
–15–
Prescaler, Phase Frequency Detector (PFD), and
Charge Pump
The dual-modulus prescaler (P/P + 1) divides the RF signal
from the VCO to a lower frequency that is manageable by the
CMOS counters.
The PFD takes inputs from the R Counter and the N Counter
(N = Int + Fraction) and produces an output proportional to the
phase and frequency difference between them. Figure 4 is a
simplified schematic.
The PFD includes a delay element that sets the width of the
antibacklash pulse. The typical value for this in the ADF7011 is
3 ns. This pulse ensures that there is no dead zone in the PFD
transfer function and minimizes phase noise and reference spurs.
MUXOUT and Lock Detect
The MUXOUT pin allows the user to access various internal
points in the ADF7011. The state of MUXOUT is controlled
by Bits M1 to M4 in the function register.
Regulator Ready
This is the default setting on MUXOUT after the transmitter
has been powered up. The power-up time of the regulator is
typically 50 µs. Since the serial interface is powered from the
regulator, it is necessary for the regulator to be at its nominal
voltage before the ADF7011 can be programmed. The status
of the regulator can be monitored at MUXOUT. Once the
Regulator Ready signal on MUXOUT is high, programming of
the ADF7011 may begin.
CP OUTPUT
R DIVIDER
N DIVIDER
R DIVIDER
N DIVIDER
HI
HI
D1
D2
Figure 4. PFD Stage
CLR1
CLR2
U1
U2
Q1
Q2
UP
DOWN
U3
ADF7011
CP
V
GND
P
CHARGE
PUMP
CP