afct-5942tltgz Avago Technologies, afct-5942tltgz Datasheet - Page 8

• Manufacturer Part Number: afct-5942tltgz
• Description: Single Mode Sff Transceivers For Sonet Oc-48/sdh Stm-16 Singlerate Operation Part Of The Avago Technologies? Metrak Family
• Manufacturer: Avago Technologies

Data Line Interconnections
Avago Technologies’ AFCT-5942xxxZ fiber-optic trans-
ceivers are designed to couple to +3.3 V PECL signals.
The transmitter driver circuit regulates the output optical
power. The regulated light output will maintain a con-
stant output optical power provided the data pattern is
balanced in duty cycle. If the data duty cycle has long,
continuous state times (low or high data duty cycle),
then the output optical power will gradually change its
average output optical power level to its preset value.
The AFCT-5942xxxZ has a transmit disable function which
is a single-ended +3.3 V TTL input which is dc-coupled to
pin 13. In addition the devices offer the designer the op-
tion of monitoring the laser diode bias current and the
laser diode optical power.
The receiver section is internally ac-coupled between
the preamplifier and the post-amplifier stages. The Data
and Data-bar outputs of the post-amplifier are internally
biased and ac-coupled to their respective output pins
(pins 9, 10).
Figure 7. Recommended Board Layout Hole Pattern
8
( 0.299)
( 0.525)
13.34
7.59
2 x Ø 2.29 MAX .
( 0.118)
3
( 0.09)
( 0.055 ±0.004)
2 x Ø 1.4 ±0.1
*4
( 0.236)
( 0.118)
6
3
( 0.28)
7.11
( 0.35)
8.89
( 0.18)
4.57
2 x Ø 1.4 ±0.1
( 0.055 ±0.004)
9 x 1.78
( 0.07)
( 0.63)
16
( 0.121)
3.08
( 0.079)
( 0.14)
3.56
2
10.16
(0 .4)
( 0.378)
9.59
20 x Ø 0.81 ±0.1
( 0.032 ±0.004)
2 x Ø 2.29
( 0.09)
output signal that is dc-coupled to pin 8 of the module.
Signal Detect should not be ac-coupled externally to the
follow-on circuits because of its infrequent state changes.
The designer also has the option of monitoring the PIN
photo detector bias current. Figure 6 shows a resistor
network, which could be used to do this. Note that the
photo detector bias current pin must be connected to V
Avago Technologies also recommends that a decoupling
capacitor is used on this pin.
Caution should be taken to account for the proper inter-
con-nection between the supporting Physical Layer inte-
grated circuits and these transceivers. Figure 6 illustrates
a recommended interface circuit for interconnecting to a
+3.3 V dc PECL fiber-optic transceiver.
Signal Detect is a single-ended, +3.3 V TTL compatible
( 0.055 ±0.004)
4 x Ø 1.4 ±0.1
( 0.079)
2
*5
DIMENSIONS IN MILLIMETERS (INCHES)
NOTES:
1. THIS
2. THE HATCHED AREAS ARE KEEP-OUT AREAS
3. 2 x 10 TRANSCEIVER MODULE REQUIRES 26
*4. THE MOUNTING STUDS SHOULD BE
*5. HOLES FOR OPTIONAL HOUSING LEADS
RECOMMENDED CIRCUIT BOARD LAYOUT
FOR THE SFF TRANSCEIVER.
RESERVED FOR HOUSING STANDOFFS. NO
METAL TRACES OR GROUND CONNECTION
IN KEEP-OUT AREAS.
PCB HOLES (20 I/O PINS, 2 SOLDER POSTS
AND 4 OPTIONAL PACKAGE GROUNDING
TABS). PACKAGE GROUNDING TABS
SHOULD BE CONNECTED TO SIGNAL
GROUND.
SOLDERED TO CHASSIS GROUND FOR
MECHANICAL INTEGRITY AND TO ENSURE
FOOTPRINT COMPATIBILITY WITH OTHER
SFF TRANSCEIVERS.
MUST BE TIED TO SIGNAL GROUND.
FIGURE
DESCRIBES
THE
CC
.