afct-5805amz Avago Technologies, afct-5805amz Datasheet - Page 3

• Manufacturer Part Number: afct-5805amz
• Description: 155 Mb/s Single Mode Fiber Optic Transceiver For Atm, Sonet Oc-3/sdh Stm-1
• Manufacturer: Avago Technologies

Recommended Circuit Schematic
In order to ensure proper functionality of the AFCT-
5805xxxZ a recommended circuit is provided in Figure
3. When designing the circuit interface, there are a few
fundamental guidelines to follow. For example, in the Rec-
ommended Circuit Schematic fi gure the diff erential data
lines should be treated as 50 ohm Microstrip or stripline
transmission lines. This will help to minimize the parasitic
inductance and capacitance eff ects. Proper termination
of the diff erential data signals will prevent refl ections and
ringing which would compromise the signal fi delity and
generate unwanted electrical noise. Locate termination
at the received signal end of the transmission line. The
length of these lines should be kept short and of equal
length. For the high speed signal lines, diff erential sig-
nals should be used, not single-ended signals, and these
diff erential signals need to be loaded symmetrically to
prevent unbalanced currents from fl owing which will
cause distortion in the signal.
Maintain a solid, low inductance ground plane for re-
turning signal currents to the power supply. Multilayer
plane printed circuit board is best for distribution of V
returning ground currents, forming transmission lines
and shielding, Also, it is important to suppress noise from
infl uencing the fi ber-optic transceiver performance, es-
pecially the receiver circuit. Proper power supply fi ltering
of V
Figure 3. Recommended Circuit Schematic
3
TERMINATE
AT PHY
DEVICE
INPUTS
CC
for this transceiver is accomplished by using the
R6
NO INTERNAL
CONNECTION
V
Rx
EER
1
RD
R5
V
RD
CC
C6
2
RD
R7
RD
3
R8
SD
SD
R10
4
C1
TOP VIEW
C3
TRANSCEIVER
C7
AT V
V
V
R9
Rx
CCR
5
cc
L1
FILTER
V
cc
CC
PINS
V
L2
Tx
CCT
6
C2
C4
C8
TD
7
TD
NO INTERNAL
CONNECTION
TERMINATION
TRANSCEIVER
R1
TD
R2
8
INPUTS
V
CC
C5
AT
V
R3
Tx
EET
9
CC
,
R4
TD
recommended, separate fi lter circuits shown in Figure
3 for the transmitter and receiver sections. These fi lter
circuits suppress V
this prevents receiver sensitivity degradation due to V
noise. It is recommended that surface-mount compo-
nents be used. Use tantalum capacitors for the 10 μF
capacitors and monolithic, ceramic bypass capacitors for
the 0.1 μF capacitors. Also, it is recommended that a sur-
face- mount coil inductor of 3.3 μH be used. Ferrite beads
can be used to replace the coil inductors when using
quieter V
over a ferrite bead. All power supply components need to
be placed physically next to the V
and transmitter. Use a good, uniform ground plane with
a minimum number of holes to provide a low-inductance
ground current return for the power supply currents.
In addition to these recommendations, Avago Tech-
nologies Application Engineering staff is available for
consulting on best layout practices with various vendors
mux/demux, clock generator and clock recovery circuits.
Avago Technologies has participated in several reference
design studies and is prepared to share the fi ndings of
these studies with interested customers. Contact your
local Avago Technologies sales representative to arrange
for this service.
NOTES:
THE SPLIT-LOAD TERMINATIONS FOR PECL SIG-
NALS NEED TO BE LOCATED AT THE INPUT OF
DEVICES RECEIVING THOSE PECL SIGNALS.
RECOMMEND 4-LAYER PRINTED CIRCUIT BOARD
WITH 50  MICROSTRIP SIGNAL PATHS BE USED.
R1 = R4 = R6 = R8 = R10 = 130  FOR +5.0V OP-
ERATION, 82  FOR +3.3V OPERATION.
R2 = R3 = R5 = R7 = R9 = 82  FOR +5.0V OPERA-
TION, 130  FOR +3.3V OPERATION.
C1 = C2 = 10 μF
C3 = C4 = C7 = C8 = 100 nF
C5 = C6 = 0.1 μF
L1 = L2 = 3.3 μH COIL OR FERRITE INDUCTOR.
CC
supplies, but a coil inductor is recommended
CC
noise over a broad frequency range,
CC
pins of the receiver
CC