as5045 austriamicrosystems, as5045 Datasheet - Page 11

• Manufacturer Part Number: as5045
• Description: 12-bit Programmable Magnetic Rotary Encoder
• Manufacturer: austriamicrosystems

AS5045 12-BIT PROGRAMMABLE MAGNETIC ROTARY ENCODER
8
The alignment mode simplifies centering the magnet over
the center of the chip to gain maximum accuracy.
Alignment mode can be enabled with the falling edge of
CSn while Prog = logic high (Figure 13). The Data bits
D9-D0 of the SSI change to a 12-bit displacement
amplitude output. A high value indicates large X or Y
displacement, but also higher absolute magnetic field
strength. The magnet is properly aligned, when the
difference between highest and lowest value over one full
turn is at a minimum.
Under normal conditions, a properly aligned magnet will
result in a reading of less than 128 over a full turn.
The MagINCn and MagDECn indicators will be = 1 when
the alignment mode reading is < 128. At the same time,
both hardware pins MagINCn (#1) and MagDECn (#2) will
be pulled to VSS. A properly aligned magnet will
therefore produce a MagINCn = MagDECn = 1 signal
throughout a full 360° turn of the magnet.
Stronger magnets or short gaps between magnet and IC
may show values larger than 128. These magnets are
still properly aligned as long as the difference between
highest and lowest value over one full turn is at a
minimum.
The Alignment mode can be reset to normal operation by
a power-on-reset (disconnect / re-connect power supply)
or by a falling edge on CSn with Prog = low.
9
The AS5045 operates either at 3.3V ±10% or at 5V
±10%. This is made possible by an internal 3.3V Low-
Dropout (LDO) Voltage regulator. The internal supply
voltage is always taken from the output of the LDO,
meaning that the internal blocks are always operating at
3.3V.
Revision 1.2, 03-Oct-06
Prog
CSn
Prog
CSn
Alignment Mode
3.3V / 5V Operation
Figure 13: Enabling the alignment mode
2µs
min.
Figure 14: Exiting alignment mode
exit AlignMode
2µs
min.
AlignMode enable
Read-out
via SSI
Read-out
via SSI
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For 3.3V operation, the LDO must be bypassed by
connecting VDD3V3 with VDD5V (see Figure 15).
For 5V operation, the 5V supply is connected to pin
VDD5V, while VDD3V3 (LDO output) must be buffered by
a 1...10µF capacitor, which is supposed to be placed
close to the supply pin (see Figure 15).
The VDD3V3 output is intended for internal use only It
must not be loaded with an external load.
The output voltage of the digital interface I/O’s
corresponds to the voltage at pin VDD5V, as the I/O
buffers
15).
A buffer capacitor of 100nF is recommended in both
cases close to pin VDD5V. Note that pin VDD3V3 must
always be buffered by a capacitor. It must not be left
floating, as this may cause an instable internal 3.3V
supply voltage which may lead to larger than normal jitter
of the measured angle.
Figure 15: Connections for 5V / 3.3V supply voltages
4.5 - 5.5V
3.0 - 3.6V
5V Operation
3.3V Operation
100n
VDD5V
VDD5V
are
VSS
VSS
supplied
LDO
LDO
VDD3V3
VDD3V3
from
this
1...10µF
Internal
VDD
N
R
C
Internal
VDD
N
R
C
T
E
F
A
E
T
E
F
A
E
I
I
pin
(see
Page 11 of 23
DO
PWM
CLK
CSn
Prog
DO
PWM
CLK
CSn
Prog
Figure
100n