lc5256b-75t128i Lattice Semiconductor Corp., lc5256b-75t128i Datasheet - Page 7

• Manufacturer Part Number: lc5256b-75t128i
• Description: 2.5v In-system Programmable Superwide High Density Plds Tm
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
For more information on the sysIO capability, please refer to technical note number TN1000, sysIO Design and
Usage Guidelines available on the Lattice web site at www.latticesemi.com.
Table 2. ispMACH 5000B Supported I/O Standards
GLB Clock Distribution
The ispLSI 5000B family has four dedicated clock input pins: GCLK0-GCLK3. These feed the Global Clock MUX,
which generates the four global clock signals (CLK0-CLK3). The global clock MUX allows a variety of combinat-
tions of complementary forms of the clock to be used within the device. Additionally, the ispMACH 5000B clock dis-
tribution network offers a differential pair of clock inputs into the global clock MUX for added flexibility. Figure 7
shows the global clock MUX.
The global clock pins are arranged in two pairs, GCLK0 and GCLK1 signals are in one pair and GCLK2 and
GCLK3 signals are in the other pair. The pins are arranged on the die such that each pair of external clock signals
can generate one internal clock from either side of the die when used in differential inputs. This arrangement allows
the clock pins to be used either as four single ended clock signals or two differential (LVPECL or LVDS) clock sig-
nal. Both polarities of the clock are available to drive the internal clock distribution networks.
LVTTL
LVCMOS 3.3
LVCMOS 2.5
LVCMOS 1.8
PCI 3.3
AGP-1X
SSTL3, Class I, II
SSTL2, Class I, II
CTT 3.3
CTT 2.5
HSTL, Class I
HSTL, Class III
GTL+
sysIO Standard
7
V
3.3V
3.3V
2.5V
1.8V
3.3V
3.3V
3.3V
2.5V
3.3V
2.5V
1.5V
1.5V
N/A
CCO
1.25V
1.25V
0.75V
V
1.5V
1.5V
1.0V
N/A
N/A
N/A
N/A
N/A
N/A
0.9
REF
ispMACH 5000B Family Data Sheet
1.25V
1.25V
0.75V
0.75V
1.5V
1.5V
1.5V
N/A
N/A
N/A
N/A
N/A
N/A
V
TT