ak4528 AKM Semiconductor, Inc., ak4528 Datasheet - Page 18

• Manufacturer Part Number: ak4528
• Description: High Performance 24bit 96khz Audio Codec
• Manufacturer: AKM Semiconductor, Inc.

ASAHI KASEI
The serial control interface is enabled by the P/S pin = “L”. The internal registers are written by the 3-wire µP interface
pins: CSN, CCLK, CDTI. The data on this interface consists of Chip address (2bits, fixed to C0/1 = “01”) Read/Write
(1bit, fixed to “1”), Register address (MSB first, 5bits) and Control data (MSB first, 8bits). Address and data is clocked in
on the rising edge of CCLK. Data is latched after a low-to-high transition of CSN. The maximum clock speed of the
CCLK is 5MHz. The CSN should be “H” if no access. The chip address is fixed to “10”. Writing is invalid for the access
to the chip address except for “10”. PDN = “L” resets the registers to their default values.
When PDN = “L”, internal registers are initialized. In case of changing P/S pin, please set PDN = “L” to reset the device.
In case of serial mode, the internal timings are initialized by RSTN = “0”, but the contents of registers are hold.
MS0011-E-01
Serial Control Interface
*AK4528 does not support the READ. C1, C0 and R/W are fixed (“101”).
CCLK
CSN
CDTI
Function
Double speed
De-emphasis
SMUTE
Output Digital ATT
HPF off
MCLK;
16/20/24bit LSB justified format
768fs@Normal
C1 C0
384fs@Double
0
Table 7. Function list (O: available, X: not available)
1
C1-C0:
R/W:
A4-A0:
D7-D0:
R/W
2
A4
3
Speed
Speed
Figure 9. Control I/F Timing
A3
Chip Address (Fixed to “10”)
READ/WRITE (Fixed to “1”:WRITE only)
Register Address
Control data
4
A2
5
A1 A0
6
- 18 -
7
D7 D6 D5 D4 D3 D2 D1 D0
8
Parallel mode
9
O
O
X
X
X
X
X
10 11 12 13 14 15
Serial mode
O
O
O
O
O
O
O
[AK4528]
2004/01