ak4645 ETC-unknow, ak4645 Datasheet
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ak4645 Summary of contents
Page 1
... The AK4645 is a stereo CODEC with a built-in Microphone-Amplifier and Headphone-Amplifier. The AK4645 features analog mixing circuits and PLL that allows easy interfacing in mobile phone and portable A/V player designs. The AK4645 is available in a 32pin QFN, utilizing less board space than competitive offerings. ...
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... HPF MIC-Amp Reduction PMADR or PMMICR PMAINR2 PMAINL2 PMAINR3 PMAINL3 PMMIN PMDAC DATT Bass D/A ALC SMUTE Boost HVSS Figure 1. Block Diagram - 2 - [AK4645 DSP Mode TVDD I2C CSN Control Register CCLK CDTI PDN Stereo ALC Separation BICK LRCK SDTO SDTI Audio I/F Stereo ...
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... ASAHI KASEI Ordering Guide −30 ∼ +85°C AK4645 AKD4645 Evaluation board for AK4645 Pin Layout LIN4 / IN4+ 25 ROUT / LON 26 LOUT / LOP 27 MIN / LIN3 28 29 RIN2 / IN2− LIN2 / IN2+ 30 LIN1 / IN1− 31 RIN1 / IN1+ 32 Compatibility with AK4643/44 1. Function Function Digital I/O of µP I/F ...
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... F1B13 F1B12 PMAINL4 PMAINR3 PMAINL3 0 0 MICR3 MICL3 LOM3 RINR4 LINL4 0 HPM3 RINH4 LINH4 These bits are added in the AK4645 [AK4645] AK4645 TVDD HVSS HVDD HPR HPL MUTET RIN4 / IN4− LIN4 / IN4+ ROUT/LON LOUT/LOP PMLO PMDAC ...
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... Note 1. All input pins except analog input pins (MIN/LIN3, LIN1, RIN1, LIN2, RIN2, RIN3, RIN4, LIN4) should not be left floating. Note 2. AVDD or AVSS voltage should be input to I2C pin. MS0543-E-00 PIN/FUNCTION Function 2 C Bus, “L”: 3-wire Serial 2 C Bus Mode Bus Mode Bus Mode [AK4645] 2006/09 ...
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... AVDD −0.3 DVDD −0.3 TVDD −0.3 HVDD ∆GND IIN −0.3 VINA −0.3 VIND −30 Ta −65 Tstg Symbol min AVDD 2.6 DVDD 2.6 TVDD 1.6 HVDD 2.6 −0.3 AVDD−DVDD - 6 - [AK4645] max Units 6.0 V 6.0 V 6 0.3 V ± AVDD+0.3 V TVDD+0.3 V °C 85 °C 150 typ max Units 3.3 3.6 V 3.3 3 ...
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... ADC → IVOL, IVOL=0dB, ALC=OFF - (Note 11) 0.168 (Note 12) 1. (Note 11) 76 (Note 12) - (Note 11) 76 (Note 12) - (Note 11) 75 (Note 12) - (Note 11) - (Note 12 [AK4645] typ max Units 60 80 kΩ kΩ + + + 0.228 Vpp - 0.114 Vpp - 0.057 Vpp 2.47 2 ...
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... Note 14. Output voltage is proportional to AVDD voltage. Vout = (LOP) − (LON) = 1.2 x AVDD (typ)@LOVL bit = “0”. MS0543-E-00 min typ - - =10kΩ (Single-ended) L 1.78 1.98 2.25 2. 100 - 0 =10kΩ for each pin (Full-differential) L 3.52 3.96 4.50 5. [AK4645] max Units 16 Bits 2.18 Vpp 2.75 Vpp - dBFS - 0 kΩ 4.36 Vpp 5.50 Vpp - dBFS - dB - kΩ 2006/09 ...
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... (Note 16) 80 (Note 17) - (Note 16) 65 (Note 17) - (Note 16) - (Note 17 =22.8Ω. L =100Ω. L HPL/HPR pin Measurement Point 47µF 6.8Ω 0.22µF C1 10Ω Figure 2. Headphone-Amp output circuit - 9 - [AK4645] typ max Units 1.98 2.38 Vpp 3.00 3.60 Vpp 1.0 - Vrms 1.06 - Vrms 70 - dBFS 80 - dBFS 20 - dBFS 70 - dBFS ...
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... Units - Vpp +4 −15 Vpp +4 +4 Vpp −1 +4 −1 µA 100 2006/09 ...
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... [AK4645 4.4 1.8 0.03 0.2 21.2 0 3.8 1.8 0.03 5 35 22.8 0 5.5 1.6 0.03 0.2 24.2 0 3.5 1.5 0.03 0.2 17.3 0 8.3 2.7 0.03 5 52.9 2006/09 ...
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... Note 29. These frequency responses scale with fs high-level and low frequency signal is input, the analog output clips to the full-scale. MS0543-E-00 FILTER CHARACTERISTICS Symbol min 26 ∆ 25 [AK4645] typ max Units - 17.3 kHz 19.4 - kHz 19.9 - kHz 22.1 - kHz - - kHz ±0 1/fs µ 19.6 kHz 20.0 - kHz 22.05 - kHz - - kHz ±0. ...
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... Duty 45 tBCK 1/(64fs) tBCKL 0.4 x tBCK tBCKH 0.4 x tBCK - 13 - [AK4645] typ max Units - - 30%TVDD V - 25%TVDD 0 0.4 V ±10 µA - =20pF; unless otherwise specified) L typ max Units ...
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... Duty - 50 tBCK - 1/(32fs) tBCK - 1/(64fs) dBCK - [AK4645] max Units 48 kHz 1/fs − tBCK 1/(32fs kHz 1/fs − tBCK 12.288 MHz 13.312 MHz 13.312 MHz ...
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... S) −40 tMBLR - −70 tLRD - −70 tBSD - tSDH 50 - tSDS 50 - tLRB 50 - tBLR 50 - tLRD - - tBSD - - tSDH 50 - tSDS [AK4645] max Units 0.5 x tBCK + 40 ns 0.5 x tBCK + ...
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... registered trademark of Philips Semiconductors. Note 34. Data must be held long enough to bridge the 300ns-transition time of SCL. Note 35. The AK4645 can be reset by the PDN pin = “L”. Note 36. This is the count of LRCK “↑” from the PMADL or PMADR bit = “1”. ...
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... Figure 4. Audio Interface Timing (PLL/EXT Master mode, DSP mode, MSBS = “0”) MS0543-E-00 1/fCLK tCLKL 1/fs tLRCKH tLRCKL Duty = tLRCKH 100 tLRCKL 100 1/fMCK tMCKL dMCK = tMCKL x fMCK x 100 tLRCKH tBCK tDBF dBCK tBSD MSB tSDS tSDH - 17 - [AK4645] VIH VIL 50%TVDD 50%TVDD 50%TVDD 50%TVDD 50%TVDD 50%TVDD VIH VIL 2006/09 ...
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... BICK SDTO SDTI Figure 6. Audio Interface Timing (PLL/EXT Master mode, Except DSP mode) MS0543-E-00 tLRCKH tBCK tDBF dBCK tBSD tSDS tBCKL tLRD tBSD tSDS tSDH - 18 - [AK4645] 50%TVDD 50%TVDD 50%TVDD 50%TVDD MSB tSDH VIH VIL 50%TVDD 50%TVDD 50%TVDD VIH VIL 2006/09 ...
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... Figure 8. Clock Timing (PLL Slave mode; PLL Reference Clock = LRCK or BICK pin, DSP mode, MSBS = “1”) MS0543-E-00 1/fs tLRCKH tBLR tBCK tBCKH tBCKL 1/fs tLRCKH tBLR tBCK tBCKH tBCKL - 19 - [AK4645] VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL 2006/09 ...
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... Duty = tLRCKH 100 = tLRCKL 100 tBCK tBCKL fMCK tMCKL dMCK = tMCKL x fMCK x 100 tLRCKH tLRB tBSD MSB tSDH tSDS MSB - 20 - [AK4645] VIH VIL VIH VIL VIH VIL 50%TVDD VIH VIL VIH VIL VIH VIL 50%TVDD VIH VIL 2006/09 ...
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... Figure 12. Clock Timing (EXT Slave mode) MS0543-E-00 tLRCKH tBSD tSDS 1/fCLK tCLKH tCLKL 1/fs Duty = tLRCKH 100 tLRCKH tLRCKL tLRCKL 100 tBCK tBCKH tBCKL - 21 - [AK4645] VIH VIL VIH VIL VIH VIL 50%TVDD MSB tSDH VIH MSB VIL VIH VIL VIH VIL ...
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... Figure 13. Audio Interface Timing (PLL/EXT Slave mode, Except DSP mode) CSN CCLK CDTI Figure 14. WRITE Command Input Timing MS0543-E-00 tLRB tBSD MSB tSDS tSDH tCSS tCCKL tCCKH tCCK tCDS tCDH [AK4645] VIH VIL VIH VIL 50%TVDD VIH VIL VIH VIL VIH VIL VIH R/W VIL 2006/09 ...
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... Figure 15. WRITE Data Input Timing tHIGH tF tHD:DAT tSU:DAT tSU:STA Start 2 Figure 16 Bus Mode Timing tPDV Figure 17. Power Down & Reset Timing 1 tPD Figure 18. Power Down & Reset Timing [AK4645] tCSW VIH VIL VIH VIL VIH VIL VIH VIL tSP VIH VIL tSU:STO Stop ...
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... AK4645 goes to master mode by changing M/S bit = “1”. When the AK4645 is used by master mode, LRCK and BICK pins are a floating state until M/S bit becomes “1”. LRCK and BICK pins of the AK4645 should be pulled-down or pulled-up by the resistor (about 100kΩ) externally to avoid the floating state ...
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... When PMPLL bit is “1”, a fully integrated analog phase locked loop (PLL) generates a clock that is selected by the PLL3-0 and FS3-0 bits. The PLL lock time is shown in Table 5, whenever the AK4645 is supplied to a stable clocks after PLL is powered-up (PMPLL bit = “0” → “1”) or sampling frequency changes. When AIN3 bit = “1”, the PLL is not available ...
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... Invalid “L” Output See Table 10 MCKO pin MCKO bit = “0” “1” “L” Output “L” Output “L” Output - 26 - [AK4645] Default N/A BICK pin LRCK pin “L” Output “L” Output Invalid Invalid See Table 11 1fs Output “ ...
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... DSP or µP 256fs/128fs/64fs/32fs MCLK 32fs, 64fs BCLK 1fs LRCK SDTI SDTO Figure 19. PLL Master Mode PS1 bit PS0 bit MCKO pin 0 0 256fs 0 1 128fs 1 0 64fs 1 1 32fs BICK Output Frequency 0 32fs Default 1 64fs - 27 - [AK4645] Default 2006/09 ...
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... PLL Slave Mode (AIN3 bit = “0”, PMPLL bit = “1”, M/S bit = “0”) A reference clock of PLL is selected among the input clocks to MCKI, BICK or LRCK pin. The required clock to the AK4645 is generated by an internal PLL circuit. Input frequency is selected by PLL3-0 bits (see Table 5). a) PLL reference clock: MCKI pin BICK and LRCK inputs should be synchronized with MCKO output ...
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... The external clocks (MCKI, BICK and LRCK) should always be present whenever the ADC or DAC is in operation (PMADL bit = “1”, PMADR bit = “1” or PMDAC bit = “1”). If these clocks are not provided, the AK4645 may draw excess current and it is not possible to operate properly because utilizes dynamic refreshed logic internally. If the external clocks are not present, the ADC and DAC should be in the power-down mode (PMADL=PMADR=PMDAC bits = “ ...
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... The external clocks (MCKI, BICK and LRCK) should always be present whenever the ADC or DAC is in operation (PMADL bit = “1”, PMADR bit = “1” or PMDAC bit = “1”). If these clocks are not provided, the AK4645 may draw excess current and it is not possible to operate properly because utilizes dynamic refreshed logic internally. If the external clocks are not present, the ADC and DAC should be in the power-down mode (PMADL=PMADR=PMDAC bits = “ ...
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... EXT Master Mode (PMPLL bit = “0”, M/S bit = “1”) The AK4645 becomes EXT Master Mode by setting PMPLL bit = “0” and M/S bit = “1”. Master clock is input from MCKI pin, the internal PLL circuit is not operated. The clock required to operate is MCKI (256fs, 512fs or 1024fs). The input frequency of MCKI is selected by FS1-0 bits (see Table 14) ...
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... ASAHI KASEI System Reset Upon power-up, the AK4645 should be reset by bringing the PDN pin = “L”. This ensures that all internal registers reset to their initial values. The ADC enters an initialization cycle that starts when the PMADL or PMADR bit is changed from “0” to “1” at PMDAC bits is “ ...
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... Rch Rch Rch 1/ [AK4645 ...
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... Rch Rch Rch 1/ [AK4645 ...
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... Don't Care Lch Data Figure 30. Mode 2 Timing - 35 - [AK4645 ...
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... Lch Data Figure 31. Mode 3 Timing MIX bit ADC Lch data x All “0” x Rch Input Signal x Lch Input Signal 0 Lch Input Signal 1 (L+R)/ [AK4645 ...
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... ASAHI KASEI MIC/LINE Input Selector The AK4645 has input selector for MIC-Amp. When MDIF1 and MDIF2 bits are “0”, INL1-0 and INR1-0 bits select LIN1/LIN2/LIN3/LIN4 and RIN1/RIN2/RIN3/RIN4, respectively. When MDIF1 and MDIF2 bits are “1”, LIN1, RIN1, LIN2 and RIN2 pins become IN1−, IN1+, IN2+ and IN2− pins respectively. In this case, full-differential input is available (Figure 33). When full-differential input is used, the signal should not be input to the pins marked by “ ...
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... Figure 32. Mic/Line Input Selector MPWR pin MIC-Amp IN1− pin IN1+ pin A/D INL0 bit INR1 bit INR0 bit [AK4645] ADC Lch ADC Rch These blocks are not available at PLL mode. AK4645 SDTO pin Lch Rch 1 IN1+/− RIN2 1 LIN2 RIN2 2006/09 ...
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... ASAHI KASEI MIC Gain Amplifier The AK4645 has a gain amplifier for microphone input. The gain of MIC-Amp is selected by the MGAIN1-0 bits (see Table 23). The typical input impedance is 60kΩ(typ)@MGAIN1-0 bits = “00” or 30kΩ(typ)@MGAIN1-0 bits = “01”, “10” or “11”. ...
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... ASAHI KASEI Digital EQ/HPF/LPF The AK4645 performs wind-noise reduction filter, stereo separation emphasis, gain compensation and ALC (Automatic Level Control) by digital domain for A/D converted data (Figure 35). FIL1, FIL3 and EQ blocks are IIR filters of 1 order. The filter coefficient of FIL3, EQ and FIL1 blocks can be set to any value. Refer to the section of “ALC operation” ...
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... Amplitude 2 − 2cos (2πf/fs) θ(f) = tan 2Bcos (2πf/fs) 1 − tan (πfc/fs tan (πfc/fs) Amplitude 2 + 2cos (2πf/fs) θ(f) = tan 2Bcos (2πf/fs [AK4645] Phase (B+1)sin (2πf/fs) − (B−1)cos (2πf/fs) Phase (B−1)sin (2πf/fs) − (B+1)cos (2πf/fs) 2006/09 ...
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... /fs tan (πfc /fs Amplitude 2ACcos (2πf/fs) θ(f) = tan 2Bcos (2πf/fs) =3000Hz, Gain=+8dB 2 fc Frequency [AK4645] 1 − tan (πfc /fs) 2 K/ tan (πfc /fs) 1 Phase (AB−C)sin (2πf/fs) − (AB+C)cos (2πf/fs) 13 2006/09 ...
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... Zero Crossing Timeout Period 8kHz 16kHz 128/fs 16ms 8ms 256/fs 32ms 16ms 512/fs 64ms 32ms 1024/fs 128ms 64ms - 43 - [AK4645] ALC Power-down Default Playback path Recording path Recording path Recording path Default 0.375dB Default 0.750dB 1.500dB 3.000dB 0.375dB 44.1kHz 2.9ms Default 5 ...
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... RGAIN0 GAIN STEP 0 1 step 0.375dB 1 2 step 0.750dB 0 3 step 1.125dB 1 4 step 1.500dB Table 32. ALC Recovery GAIN Step - 44 - [AK4645] 44.1kHz 2.9ms Default 5.8ms 11.6ms 23.2ms 46.4ms 92.9ms 185.8ms 371.5ms Default 2006/09 ...
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... Table 33. Reference Level at ALC Recovery operation RFST1 bit MS0543-E-00 GAIN(dB) Step +36.0 +35.625 +35.25 : +30.375 0.375dB +30.0 +29.625 : −53.25 −53.625 −54.0 MUTE RFST0 bit Recovery Speed 0 4 times 1 8 times 0 16times 1 N/A Table 34. Fast Recovery Speed Setting - 45 - [AK4645] Default Default 2006/09 ...
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... Limiter and Recovery Step = 1 Fast Recovery Speed = 4 step Gain of IVOL = +30dB Maximum Gain = +30.0dB Limiter Detection Level = −4.1dBFS ALC bit = “1” (1) Addr=06H, Data=14H (3) Addr=09H&0CH, Data=E1H the same or smaller than REF’ [AK4645] fs=44.1kHz Data Operation −4.1dBFS 01 0 Enable 11 23.2ms 011 23 ...
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... Even if the path is switched from recording to playback, the register setting of IVOL remains. Therefore, IVL7-0 and IVR7-0 bits should be set to “91H” (0dB). IVL7-0 IVR7-0 F1H F0H EFH : E2H E1H E0H : 03H 02H 01H 00H MS0543-E-00 GAIN (dB) Step +36.0 +35.625 +35.25 : +30.375 +30.0 0.375dB +29.625 : −53.25 −53.625 −54 MUTE Table 36. Input Digital Volume Setting - 47 - [AK4645] Default 2006/09 ...
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... When ALC is enabled again, ALC bit should be set to “1” interval more than zero crossing timeout period after ALC bit = “0”. MS0543-E-00 Enable E1H(+30dB) C6H(+20dB) E1(+30dB) --> F1(+36dB) E1(+30dB) (1) (2) E1(+30dB) --> F1(+36dB) C6H(+20dB [AK4645] Disable 2006/09 ...
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... ASAHI KASEI De-emphasis Filter The AK4645 includes the digital de-emphasis filter (tc = 50/15µs) by IIR filter. Setting the DEM1-0 bits enables the de-emphasis filter (Table 37). DEM1 Bass Boost Function The BST1-0 bits control the amount of low frequency boost applied to the DAC output signal (Table 38). If the BST1-0 bits are set to “ ...
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... ASAHI KASEI Digital Output Volume The AK4645 has a digital output volume (256 levels, 0.5dB step, Mute). The volume can be set by the DVL7-0 and DVR7-0 bits. The volume is included in front of a DAC block. The input data of DAC is changed from +12 to –115dB or MUTE. When the DVOLC bit = “1”, the DVL7-0 bits control both Lch and Rch attenuation levels. When the DVOLC bit = “ ...
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... Analog output corresponding to digital input has the group delay (GD). (3) If the soft mute is cancelled within the cycle set by the DVTM bit, the attenuation is discounted and returned to the value set by the DVL/R7-0 bits. MS0543-E- bit ( (2) Figure 39. Soft Mute Function - 51 - [AK4645] ( 2006/09 ...
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... MIN/LIN3 pin VCOC/RIN3 pin LIN4/IN4+ pin RIN4/IN4− pin Figure 40. Analog Mixing Circuit (Stereo Input) MS0543-E-00 INL1-0 bits ADC Lch MIC-Amp MDIF1 bit INR1-0 bits ADC Rch MIC-Amp MDIF2 bit These blocks are not available at PLL mode. Lineout, HP-Amp - 52 - [AK4645] 2006/09 ...
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... PMAINL3 bit PMAINR3 bit LINL3/RINR3 LOUT/LOP pin, ROUT/LON pin LINH3/RINH3 HPL, HPR pins LIN2/RIN2/LIN3/RIN3/LIN4/RIN4 LOUT/ROUT 0dB +2dB LOUT/ROUT Output Gain (typ) LIN2/RIN2/LIN3/RIN3/LIN4/RIN4 LOP/LON 0dB +2dB LOP/LON Output Gain (typ) LIN2/RIN2/LIN3/RIN3/LIN4/RIN4 HPL/HPR 0dB +3.6dB Headphone-Amp Output Gain (typ [AK4645] Default Default Default 2006/09 ...
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... MIC-Amp Rch PMAINR4 bit Lineout, HP-Amp IN4+/IN4− LOUT/ROUT −6dB −4dB LOUT/ROUT Output Gain (typ) IN4+/IN4− LOP/LON 0dB +2dB LOP/LON Output Gain (typ) IN4+/IN4− HPL/HPR −6dB Default −2.4dB Headphone-Amp Output Gain (typ [AK4645] Default Default 2006/09 ...
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... LOUT/ROUT Output Gain (typ MIN LOP/LON +6dB +8dB LOP/LON Output Gain (typ MIN HPL/HPR −20dB −16.4dB Headphone-Amp Output Gain (typ [AK4645 LOUT/RCP pin, ROUT/RCN pin HPL, HPR pin Default = 20kΩ i Default = 20kΩ i Default = 20kΩ ...
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... LOUT/ROUT pin Power-down Pull-down to AVSS Normal Operation Normal Operation Power-save Fall down to AVSS Power-save Rise up to VCOM Gain Output Voltage (typ) 0dB 0.6 x AVDD Default +2dB 0.757 x AVDD LOUT 1µF 220Ω ROUT - 56 - [AK4645] LOUT pin ROUT pin Default 20kΩ 2006/09 ...
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... LOUT and ROUT pins fall down to AVSS. Fall time is 200ms (max 300ms) at C=1µF and AVDD=3.3V. (6) Set LOPS bit = “0” after LOUT and ROUT pins fall down. Stereo line output exits the power-save mode. MS0543-E- [AK4645 ≥ 2006/09 ...
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... Figure 49. ROUT Mixing Circuit (AIN3 bit = “0”, LOVL bit = “0”) MS0543-E-00 LINL2 bit 0dB LINL4 bit M 0dB I LOUT pin MINL bit 0dB X DACL bit 0dB RINR2 bit 0dB RINR4 bit M 0dB I ROUT pin MINL bit 0dB X DACL bit 0dB - 58 - [AK4645] 2006/09 ...
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... PLL mode. DACL bit DAC Lch 0dB RINR2 bit 0dB RINR4 bit 0dB MICR3 bit RINR3 bit 0dB *These blocks are not available at PLL mode. DACL bit DAC Rch 0dB - 59 - [AK4645] M LOUT pin ROUT pin I X 2006/09 ...
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... Figure 53. Power-up/Power-down Timing for Mono Line Output MS0543-E-00 “DACL” “LOVL” Figure 52. Mono Line Output Gain Output Voltage (typ) +6dB 1.2 x AVDD +8dB 1.5 x AVDD Mode LOP Power-down Hi-Z Power-save Hi-Z Normal Operation Normal Operation - 60 - [AK4645] LOP pin LON pin Default LON Hi-Z VCOM/2 Default Normal Operation Hi-Z VCOM Hi-Z 2006/09 ...
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... PLL mode. RINR2 bit 0dB RINR4 bit 0dB MICR3 bit RINR3 bit 0dB *These blocks are not available at PLL mode. DACL bit DAC Lch 0dB DACL bit DAC Rch 0dB - 61 - [AK4645] LOP/N pin M LOP/N pin I X 2006/09 ...
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... When an external resistor R is smaller than 12Ω, put an oscillation prevention circuit (0.22µF±20% capacitor and 10Ω±20% resistor) because it has the possibility that Headphone-Amp oscillates. MS0543-E-00 0 0.6 x AVDD Table 54. Headphone-Amp Output Voltage (3) ( [AK4645] 1 0.91 x AVDD “0”: 500ms(max) is 16Ω. Output powers are shown at L 2006/09 ...
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... When PMVCM=PMHPL=PMHPR bits = “0” and HPZ bit = “1”, HP-Amp is powered-down and HPL/R pins are pulled-down to HVSS by 200kΩ (typ). In this setting available to connect HP-Amp of AK4645 and external single supply HP-Amp by “wired OR”. In this mode, power supply current is 20µA(typ). ...
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... Figure 60. HPR Mixing Circuit (AIN3 bit = “0”, HPG bit = “0”) MS0543-E-00 HPL pin Headphone HPR pin LINH2 bit 0dB LINH4 bit M 0dB I MINH bit −20dB X DACH bit 0dB RINH2 bit 0dB RINH4 bit M 0dB I MINH bit − 20dB X DACH bit 0dB - 64 - [AK4645] HPL pin HPR pin 2006/09 ...
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... PLL mode. DACH bit DAC Lch 0dB RINH2 bit 0dB RINH4 bit 0dB MICR3 bit RINH3 bit 0dB *These blocks are not available at PLL mode. DACH bit DAC Rch 0dB - 65 - [AK4645] M HPL pin HPR pin I X 2006/09 ...
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... MS0543-E- R/W “1” Chip Address; Fixed to “1” READ/WRITE (“1”: WRITE, “0”: READ); Fixed to “1” Register Address Control data Figure 63. Serial Control I/F Timing - 66 - [AK4645] 2006/09 ...
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... HIGH defines a STOP condition (Figure 70). The AK4645 can perform more than one byte write operation per sequence. After receipt of the third byte the AK4645 generates an acknowledge and awaits the next data. The master can transmit more than one byte instead of terminating the write cycle after the first data byte is transferred ...
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... ASAHI KASEI (2)-2. READ Operations Set the R/W bit = “1” for the READ operation of the AK4645. After transmission of data, the master can read the next address’s data by generating an acknowledge instead of terminating the write cycle after the receipt of the first data word. ...
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... MASTER S START CONDITION SDA SCL MS0543-E-00 Figure 70. START and STOP Conditions Figure 71. Acknowledge on the I C-Bus data line change stable; of data data valid allowed 2 Figure 72. Bit Transfer on the I C-Bus - 69 - [AK4645] P stop condition not acknowledge acknowledge 8 9 clock pulse for acknowledgement 2006/09 ...
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... F1A13 F1A12 F1B6 F1B5 F1B4 0 0 F1B13 F1B12 PMAINL4 PMAINR3 PMAINL3 0 0 MICR3 MICL3 LOM3 RINR4 LINL4 0 HPM3 RINH4 LINH4 [AK4645 PMLO PMDAC 0 PMADL M/S 0 MCKO PMPLL 0 PMMP 0 MGAIN0 0 MINL 0 0 BCKO 0 DIF1 DIF0 BCKP FS2 FS1 FS0 ...
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... PDN pin should be “L”. When neither ADC nor DAC are used, external clocks may not be present. When ADC or DAC is used, external clocks must always be present. MS0543-E- PMVCM PMMIN 0 PMLO [AK4645 PMDAC 0 PMADL 2006/09 ...
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... When PMLO bit is “1”, DACL bit is enabled. When PMLO bit is “0”, the LOUT/ROUT pins go to AVSS. MS0543-E- HPMTN PMHPL PMHPR DACL [AK4645 M/S 0 MCKO PMPLL PMMP 0 MGAIN0 ...
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... D5 D4 LOPS 0 MGAIN1 PLL3 PLL2 PLL1 PLL0 PS1 PS0 FS3 MSBS [AK4645 MINL BCKO 0 DIF1 DIF0 BCKP FS2 FS1 FS0 0 ...
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... WTM2 ZTM1 ZTM0 ALC ZELMN REF6 REF5 REF4 [AK4645 WTM1 WTM0 RFST1 RFST0 LMAT1 LMAT0 RGAIN0 LMTH0 REF3 REF2 REF1 ...
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... DVR6 DVR5 DVR4 LMTH1 LOOP SMUTE DVOLC [AK4645 IVL3 IVL2 IVL1 IVL0 IVR3 IVR2 IVR1 IVR0 DVL3 DVL2 DVL1 DVL0 DVR3 DVR2 DVR1 DVR0 1 0 ...
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... HPG: Headphone-Amp Gain Select (See Table 54.) 0: 0dB (Default) 1: +3.6dB MS0543-E- INL1 HPG MDIF2 [AK4645 IVOLC HPM MINH DACH MDIF1 INR0 INL0 PMADR 2006/09 ...
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... EQC6 EQC5 EQC4 EQC14 EQC13 EQC12 F1A7 F1A6 F1A5 F1A4 F1AS 0 F1A13 F1A12 F1B7 F1B6 F1B5 F1B4 0 0 F1B13 F1B12 [AK4645 FIL3 F3A3 F3A2 F3A1 F3A0 F3A11 F3A10 F3A9 F3A8 F3B3 F3B2 ...
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... Power down (Default) 1: Power up PMAINL4: LIN4 Mixing Circuit Power Management 0: Power down (Default) 1: Power up PMAINR4: RIN4 Mixing Circuit Power Management 0: Power down (Default) 1: Power up MS0543-E- PMAINL4 PMAINR3 PMAINL3 [AK4645 PMAINR2 PMAINL2 PMMICR PMMICL 2006/09 ...
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... MIC-Amp Lch output signal is selected. MICR3: Switch Control from MIC-Amp Rch to Analog Output 0: RIN3 input signal is selected. (Default) 1: MIC-Amp Rch output signal is selected. MS0543-E- MICR3 MICL3 [AK4645 LODIF L4DIF MIX AIN3 2006/09 ...
Page 80
... LOM3: Mono Mixing from MIC-Amp (or LIN3/RIN3) to Stereo Line Output 0: Stereo Mixing (Default) 1: Mono Mixing LOM: Mono Mixing from DAC to Stereo Line Output 0: Stereo Mixing (Default) 1: Mono Mixing MS0543-E- LOM LOM3 RINR4 LINL4 [AK4645 RINR3 LINL3 RINR2 LINL2 2006/09 ...
Page 81
... RINH4: Switch Control from RIN4 pin to Headphone Output (without MIC-Amp) 0: OFF (Default HPM3: Mono Mixing from MIC-Amp (or LIN3/RIN3) to Headphone Output 0: Stereo Mixing (Default) 1: Mono Mixing MS0543-E- HPM3 RINH4 LINH4 [AK4645 RINH3 LINH3 RINH2 LINH2 2006/09 ...
Page 82
... When the AK4645 is EXT mode (PMPLL bit = “0”), a resistor and capacitor of VCOC pin is not needed. - When the AK4645 is PLL mode (PMPLL bit = “1”), a resistor and capacitor of VCOC pin is shown in Table 5. - When the AK4645 is used at master mode, LRCK and BICK pins are floating before M/S bit is changed to “1”. ...
Page 83
... All digital input pins should not be left floating. - When AIN3 bit = “1”, PLL is not available. - When the AK4645 is used at master mode, LRCK and BICK pins are floating before M/S bit is changed to “1”. Therefore, 100kΩ around pull-up resistor should be connected to LRCK and BICK pins of the AK4645. ...
Page 84
... If AVDD, DVDD, TVDD and HVDD are supplied separately, the power-up sequence is not critical. AVSS and HVSS of the AK4645 should be connected to the analog ground plane. System analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board ...
Page 85
... PLL lock time is 40ms(max) after PMPLL bit changes from “0” to “1” and MCKI is supplied from an external source. (6) The AK4645 starts to output the LRCK and BICK clocks after the PLL becomes stable. Then normal operation starts. (7) The invalid frequency is output from MCKO pin during this period if MCKO bit = “1”. ...
Page 86
... Internal Clock <Example> (1) After Power Up: PDN pin “L” “L” time of 150ns or more is needed to reset the AK4645. (2) DIF1-0, FS3-0 and PLL3-0 bits should be set during this period. (3) Power Up VCOM: PMVCM bit = “0” VCOM should first be powered up before the other block operates. ...
Page 87
... LRCK pin <Example> (1) After Power Up: PDN pin “L” “L” time of 150ns or more is needed to reset the AK4645. (2) DIF1-0, PLL3-0 and FS3-0 bits should be set during this period. (3) Power Up VCOM: PMVCM bit = “0” VCOM should first be powered up before the other block operates. ...
Page 88
... BICK pin <Example> (1) After Power Up: PDN pin “L” “L” time of 150ns or more is needed to reset the AK4645. (2) DIF1-0 and FS1-0 bits should be set during this period. (3) Power Up VCOM: PMVCM bit = “0” VCOM should first be powered up before the other block operates. ...
Page 89
... BICK pin <Example> (1) After Power Up: PDN pin “L” “L” time of 150ns or more is needed to reset the AK4645. (2) MCKI should be input. (3) After DIF1-0 and FS1-0 bits are set, M/S bit should be set to “1”. Then LRCK and BICK are output. (4) Power Up VCOM: PMVCM bit = “0” ...
Page 90
... Registers set-up sequence at ALC operation” At first, clocks should be supplied according to “Clock Set Up” sequence. (1) Set up a sampling frequency (FS3-0 bit). When the AK4645 is PLL mode, MIC and ADC should be powered-up in consideration of PLL lock time after a sampling frequency is changed. (2) Set up MIC input (Addr: 02H) ...
Page 91
... At first, clocks should be supplied according to “Clock Set Up” sequence. (1) Set up a sampling frequency (FS3-0 bits). When the AK4645 is PLL mode, DAC and Headphone-Amp should be powered-up in consideration of PLL lock time after a sampling frequency is changed. (2) Set up the path of “DAC → HP-Amp”: DACH bit = “0” → “1” ...
Page 92
... ROUT pin <Example> At first, clocks should be supplied according to “Clock Set Up” sequence. (1) Set up the sampling frequency (FS3-0 bits). When the AK4645 is PLL mode, DAC and Stereo Line-Amp should be powered-up in consideration of PLL lock time after the sampling frequency is changed. (2) Set up the path of “DAC (3) Set up the input digital volume (Addr: 09H and 0CH) When PMADL = PMADR bits = “ ...
Page 93
... Figure 84. Clock Stopping Sequence (2) Example Audio I/F Format: MSB justified (ADC & DAC) PLL Reference clock: MCKI BICK frequency: 64fs Sampling Frequency: 8kHz Figure 85. Clock Stopping Sequence ( [AK4645] (1) Addr:01H, Data:00H (2) Stop the external clocks (1) Addr:01H, Data:00H (2) Stop the external clocks 2006/09 ...
Page 94
... Sampling Frequency:8kHz Figure 86. Clock Stopping Sequence (4) Example Audio I/F Format :MSB justified(ADC & DAC) Input MCKI frequency:1024fs "H" or "L" Sampling Frequency:8kHz "H" or "L" Figure 87. Clock Stopping Sequence ( [AK4645] (1) Stop the external clocks (1) Stop the external MCKI 2006/09 ...
Page 95
... Note) The exposed pad on the bottom surface of the package must be open or connected to the grournd. Material & Lead finish Package molding compound: Lead frame material: Lead frame surface treatment: MS0543-E-00 PACKAGE 0.40 ± 0. C0. Epoxy Cu Solder (Pb free) plate - 95 - [AK4645] Exposed Pad 32 1 3.5 2006/09 ...
Page 96
... AKM harmless from any and all claims arising from the use of said product in the absence of such notification. MS0543-E-00 MARKING AKM AK4645 XXXXX 1 XXXXX : Date code identifier (5 digits) Revision History Page Contents IMPORTANT NOTICE - 96 - [AK4645] 2006/09 ...