ak4632 AKM Semiconductor, Inc., ak4632 Datasheet
ak4632
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ak4632 Summary of contents
Page 1
... Amplifier. Input circuits include a Microphone-Amplifier and an ALC (Automatic Level Control) circuit. Output circuits include a Speaker-Amplifier and Mono Line Output. Video circuits include a LPF and Video-Amplifier. The AK4632 suits a moving picture of Digital Still Camera and etc. This speaker-Amplifier supports a Piezo Speaker. The AK4632 is housed in a space-saving 32-pin QFN package ...
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... ADC HPF Audio Interface ALC1A PMDAC DACA DAC DVOL BEEPA ALC1M DACM PMSPK ALC2 LPF PLL CLAMP MIN MOUT VIN Figure 1. AK4632 Block Diagram - 2 - [AK4632] ~ 13kHz (1024fs AVSS AVDD DVDD DVSS PDN FCK BICK SDTO DSP SDTI and uP CSN Control ...
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... Video Function Package The audio function of the AK4632 is compatible with that of the AK4631. Since the register map of audio function is the same as the AK4631’s, the software of the audio function can run on the ak4632 without any change. MS0396-E-00 32pin QFN (0.5mm pitch) ...
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... Bias voltage of ADC inputs and DAC outputs. Note : All input pins except analog input pins (MIC, AIN, MIN, BEEP and VIN pins) should not be left floating. Note : The exposed pad on the bottom surface of the package must be open. MS0396-E-00 PIN/FUNCTION Function - 4 - [AK4632] 2005/06 ...
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... Note 3. MIC, AIN, BEEP, MIN pins Note 4. VIN pin Note 5. In case that PCB wiring density is 100%. This power is the AK4632 internal dissipation that does not include power of externally connected speaker. WARNING: Operation at or beyond these limits may result in permanent damage to the device. ...
Page 6
... When the power supplies are partially powered OFF, the AK4632 must be reset by bringing PDN pin “L” after these power supplies are powered ON again. Note 7. SVDD = 2.6 ∼ 3.6V when 8Ω dynamic speaker is connected to the AK4632. If SVDD is more than 3.6V when 8Ω dynamic speaker is connected to the AK4632, the output of Speaker-Amp should be restricted in consideration of maximum power dissipation as the following ...
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... Note 13. Output voltage is proportional to AVDD voltage. Vout = 0.6 x AVDD (typ) MS0396-E-00 ANALOG CHRACTERISTICS min 2. 0.05 −8 IPGA ADC, MIC Gain=20dB, IPGA=0dB, ALC1=OFF - 0.168 =10kΩ [AK4632] typ max Units 30 40 kΩ 2.47 2. kΩ kΩ 0.5 ...
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... Note 21. Output Voltage is proportional to AVDD voltage. Vout = 0.6 x AVDD (typ) MS0396-E-00 min SPP/SPN, ALC2=OFF, R 2.47 3. SPP/SPN pins, ALC2=OFF, C =3µ 6. 0. [AK4632] typ max Units =8Ω, BTL, SVDD=3.3V L 3.09 3.71 Vpp 4.00 4.80 Vpp Ω =10Ω BTL, SVDD=5.0V serial 6 ...
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... Note 24. R1 and C2 compose of Low Pass Filter(LPF) in Figure 2. The cut off frequency of LPF is 10.6MHz 400pF. Video Signal Output MS0396-E-00 min - - 5.0 2 (Note 23) 140 - - -3 0 ohm C1 C2 Figure 2. Load Capacitance C1 and [AK4632] typ max Units 1.2 - Vpp µA 2.0 - 6.0 7.0 dB 2.52 - Vpp 2.4 - Vpp 2.4 - Vpp 0. - Ω 150 - - ...
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... Note 25. PLL Master Mode (MCKI=12.288MHz) and PMV=PMMIC = PMADC = PMDAC = PMSPK = PMVCM = PMPLL = MCKO = PMAO = PMBP = MPWR = M/S =“1”. And output current from MPI pin is 0mA. When the AK4632 is EXT mode (PMPLL = MCKO = M/S = “0”), “AVDD+DVDD” is typically 7mA@fs=8kHz, 9.5mA@fs=48kHz). ...
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... L typ max Units - 27.0 MHz - - kHz kHz 0.5 x tBCK + ...
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... S mode) tFSD - tBSD - tSDH 50 tSDS [AK4632] typ max Units 8 26 kHz - 1/fFCK-tBFCK 1/16fFCK kHz - 1/fFCK-tBFCK 1/16fFCK - ns 1/32fFCK ...
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... CCLK “↑“ to CSN “↑“ Reset Timing PDN Pulse Width (Note 34) PMADC “↑“ to SDTO valid (Note 35) Note 34. The AK4632 can be reset by the PDN pin = “L” Note 35. This is the count of FCK “↑“ from the PMADC = “1”. MS0396-E-00 Symbol min fCLK 1 ...
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... SDTI Figure 4. Audio Interface Timing (PLL Master mode & DSP mode: MSBS = “0”) MS0396-E-00 1/fCLK tCLKL 1/fFCK dFCK 1/fMCK tMCKOL tBCK tDBF dBCK tBSD MSB tSDS tSDH MSB - 14 - [AK4632] VIH VIL 50%DVDD 50%DVDD 50%DVDD 50%DVDD 50%DVDD 50%DVDD VIH VIL 2005/06 ...
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... BICK SDTO SDTI Figure 6. Audio Interface Timing (PLL Master mode & Except DSP mode) MS0396-E-00 tBCK tDBF dBCK tBSD tSDS dBCK tFSD tSDS tSDH - 15 - [AK4632] 50%DVDD 50%DVDD 50%DVDD MSB 50%DVDD tSDH VIH MSB VIL 50%DVDD 50%DVDD tBSD 50%DVDD VIH VIL ...
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... Figure 8. Clock Timing (PLL Slave mode; PLL Reference Clock = FCK or BICK pin & DSP mode; MSBS = 1) MS0396-E-00 1/fFCK tFCKH tBFCK tBCK tBCKH tBCKL 1/fFCK tFCKH tBFCK tBCK tBCKH tBCKL - 16 - [AK4632] VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL 2005/06 ...
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... BICK tBCKH MCKO tMCKOH dMCK = tMCKOL x fMCK x 100 Figure 9. Clock Timing (PLL Slave mode; PLL Reference Clock = MCKI pin & Except DSP mode) MS0396-E-00 1/fCLK tCLKL 1/fFCK tFCKL tBCK tBCKL 1/fMCK tMCKOL - 17 - [AK4632] VIH VIL VIH VIL VIH VIL 50%DVDD 2005/06 ...
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... SDTO SDTI Figure 11. Audio Interface Timing (PLL Slave mode, DSP mode; MSBS = 1) MS0396-E-00 tFCKH tFCKB tBSD MSB tSDH tSDS MSB tFCKH tBSD tSDS - 18 - [AK4632] VIH VIL VIH VIL VIH VIL 50%DVDD VIH VIL VIH VIL VIH VIL VIH VIL ...
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... SDTO SDTI Figure 13. Audio Interface Timing (PLL, EXT Slave mode & Except DSP mode) MS0396-E-00 1/fCLK tCLKL 1/fFCK tFCKL tBCK tBCKL tFCKB tBSD MSB tSDS tSDH - 19 - [AK4632] VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL 50%DVDD VIH VIL 2005/06 ...
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... C1 C0 tCSH D1 D0 Figure 15. WRITE Data Input Timing tPDV Figure 16. Power Down & Reset Timing 1 tPD Figure 17. Power Down & Reset Timing [AK4632] VIH VIL VIH VIL tCCK tCDH VIH R/W VIL tCSW VIH VIL VIH VIL ...
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... Input for PLL (Note 37) 1 256fs Output “L” Output 0 “L” Output 0 Table 2. Clock pins state in Clock Mode MCKPD bit ="0" 25kΩ AK4632 Figure 18. Pull-down resistor of MCKI pin - 21 - [AK4632] MCKPD bit Figure 0 Figure 19 0 Figure 20 1 Figure Figure ...
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... When PMPLL bit is “1”, a fully integrated analog phase locked loop (PLL) generates a clock that is selected by the PLL3-0 and FS3-0 bits. The PLL lock time is shown in Table 4, whenever the AK4632 is supplied to a stable clocks after PLL is powered-up (PMPLL bit = “0” → “1”) or sampling frequency changes. ...
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... Invalid “L” Output 256fs Output MCKO pin MCKO bit = “0” “1” “L” Output “L” Output “L” Output - 23 - [AK4632] Default N/A “1” or BICK pin FCK pin Invalid Invalid “L” Output “L” Output 1fs Output See Table 9 “ ...
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... Table 9. BICK Output Frequency at Master Mode MS0396-E-00 11.2896MHz, 12MHz, 12.288MHz 13.5MHz, 24MHz, 27MHz DSP or µ P 256fs MCLK 16fs, 32fs, 64fs BCLK 1fs FCK SDTI SDTO Figure 19. PLL Master Mode BICK Output BCKO0 Frequency 0 0 16fs 0 1 32fs 1 0 64fs [AK4632] Default 2005/06 ...
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... The external clocks (MCKI, BICK and FCK) should always be present whenever the ADC or DAC is in operation (PMADC bit = “1” or PMDAC bit = “1”). If these clocks are not provided, the AK4632 may draw excess current and it is not possible to operate properly because utilizes dynamic refreshed logic internally. If the external clocks are not present, the ADC and DAC should be in the power-down mode (PMADC bit =PMDAC bit = “ ...
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... The external clocks (MCKI, BICK and FCK) should always be present whenever the ADC or DAC is in operation (PMADC bit = “1” or PMDAC bit = “1”). If these clocks are not provided, the AK4632 may draw excess current and it is not possible to operate properly because utilizes dynamic refreshed logic internally. If the external clocks are not present, the ADC and DAC should be in the power-down mode (PMADC bit = PMDAC bit = “ ...
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... System Reset Upon power-up, reset the AK4632 by bringing the PDN pin = “L”. This ensures that all internal registers reset to their initial values. The ADC enters an initialization cycle that starts when the PMADC bit is changed from “0” to “1”. The initialization cycle time is 1059/fs, or 133ms@fs=8kHz. During the initialization cycle, the ADC digital data outputs of both channels are forced to a 2's compliment, “ ...
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... Don’t Care 1/ [AK4632 ...
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... Don’t Care 1/ [AK4632 ...
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... Don’t Care 1 0 Data 1/fs Figure 28. Mode 2 Timing - 30 - [AK4632 Don’t Care Don’t Care ...
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... The ADC has a digital high pass filter for DC offset cancellation. The cut-off frequency of the HPF is 1.25Hz (@fs=8kHz) and scales with sampling rate (fs). MIC Gain Amplifier The AK4632 has a Gain Amplifier for Microphone input. This gain is 0dB, +20dB, +26dB or +32dB, selected by the MGAIN1-0 bit. The typical input impedance is 30kΩ. MGAIN1 bit ...
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... IPGA value is attenuated at the zero-detect points of the waveform. [2] ALC1 Recovery Operation The ALC1 recovery refers to the amount of time that the AK4632 will allow a signal to exceed a predetermined limiting value prior to enabling the limiting function. The ALC1 recovery operation uses the WTM1-0 bits to define the wait period used after completing an ALC1 limiter operation. If the input signal does not exceed the “ ...
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... Don’t use 0 Enable 00 00 47H +27.5dB 10H Enable Table 15. Examples of the ALC1 Setting Example: * The value of IPGA should be the same or smaller than REF’ [AK4632] fs=16kHz Data Operation 1 -4dBFS 00 Don’t use 0 Enable 16ms 01 16ms 16ms 01 16ms 47H +27.5dB ...
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... ASAHI KASEI Digital Output Volume The AK4632 has a digital output volume (256 levels, 0.5dB step, Mute). The volume can be set by the DVOL7-0 bits. The volume is included in front of a DAC block, a input data of DAC is changed from +12 to –115dB with MUTE. This volume has a soft transition function. It takes 1061/fs or 256/fs from 00H to FFH. ...
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... AOUT pin falls down to AVSS. Fall time is 200ms (max 300ms) at C=1µF. (6) Set AOPSN bit = “0” after AOUT pin falls down. Mono line output exits the power-save mode. MS0396-E-00 1µF 220Ω AOUT ( [AK4632] 20kΩ ≥ 2005/06 ...
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... Figure 35. Zener diodes should be inserted between speaker and GND as shown in Figure 35, in order to protect SPK-Amp of AK4632 from the power that the piezo speaker outputs when the speaker is pressured. Zener diodes of the following Zener voltage should be used. ...
Page 37
... When the PMSPK bit is “1” and SPPS bit is “0”, the Speaker-amp enters power-save-mode. In this mode, the SPP pin is placed in a Hi-Z state and the SPN pin goes to SVDD/2 voltage. And then the Speaker output gradually changes to the SVDD/2 voltage and this mode can reduce pop noise at power-up. When the AK4632 is powered-down, pop noise can be also reduced by first entering power-save-mode. ...
Page 38
... Table 22. Gain of Speaker-Amp at ALC2 OFF(Full-differential Output) MS0396-E-00 ALC2 Limiter operation −5.2dBV 2/fs = 250µs 2/fs = 125µs No 0.5dB step SPKG1-0 bits Gain 00 +4.4dB 01 +6.4dB 10 +10.6dB 11 +12.7dB - 38 - [AK4632] ALC2 Recovery operation −7.2dBV 512/fs=64ms 512/fs=32ms Yes (Timeout = Period Time) 1dB step 2005/06 ...
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... ALC2 SPK-AMP FS-4dB = -7.1dBV -3.1dBV +9.9dB +9.9dB +3.9dB -4.0dB +2.0dB -11.1dBV FS-6.0dB = -9.1dBV +6.0dB -15.1dBV +14.0dB -23.1dBV ALC2 SPK-AMP - 39 - [AK4632] 0.8dBV 0dBV -1.2dBV Full-differential Single-ended -5.2dBV -10dBV -20dBV -30dBV 10dBV Full-differential 2.8dBV 0.8dBV 0dBV Single-ended -3.2dBV -10dBV -20dBV -30dBV ...
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... ALC2 SPK-AMP 9.1dBV +16.2dB +16.2dB +10.2dB -3.1dBV FS-4dB = -7.1dBV -4.0dB +2.0dB -11.1dBV FS-6.0dB = -9.1dBV +6.0dB -15.1dBV +14.0dB -23.1dBV ALC2 SPK-AMP - 40 - [AK4632] 10dBV 7.0dBV Full-differential 5.0dBV Single-ended 1.0dBV 0dBV -10dBV -20dBV -30dBV 10dBV Full-differential 7.1dBV Single-ended 3.1dBV 0dBV -10dBV -20dBV -30dBV ...
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... ASAHI KASEI Video Block Video-Amp has a drivability for a load resistance of 150Ω. The AK4632 has a composite input and output. A Low Pass Filter(LPF) and Gain Control Amp(GCA) are integrated and both DC output and Sag Compensation circuit are supported as shown in Figure 41 and Figure 42. The capacitance for Sag Compensation circuit is 100µ F+2.2µ 47µ F+1.0µ F. ...
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... R/W “1” Chip Address (C1 = “1” “0”); Fixed to “10” READ/WRITE (“1”: WRITE, “0”: READ); Fixed to “1” Register Address Control data Figure 43. Serial Control I/F Timing - 42 - [AK4632] Default 2005/06 ...
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... LMAT1 REF6 REF5 REF4 REF3 IPGA6 IPGA5 IPGA4 IPGA3 DVOL6 DVOL5 DVOL4 DVOL3 0 RFS5 RFS4 RFS3 SAGC1 SAGC0 VGCA4 VGCA3 - 43 - [AK4632 PMDAC PMMIC PMADC MCKPD MCKO PMPLL MPWR MICAD MGAIN0 BEEPA ALC1M ALC1A BCKO0 DIF1 DIF0 FS2 FS1 FS0 WTM0 ...
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... BEEP pin AOUT pin) only, the clocks may not be present. When ADC, DAC, ALC1 or ALC2 is in operation, the clocks must always be present. MS0396-E- PMVCM PMBP PMSPK PMAO SPP/SPN pins) or Mono Lineout-Amp - 44 - [AK4632 PMDAC PMMIC PMADC 2005/06 ...
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... Master Clock input enable 1: Pull down by 25kΩ (typ.) (Default) M/S: Select Master / Slave Mode 0: Slave Mode (Default) 1: Master Mode PMV: Video Block Power Control 0: Power down (Default) 1: Power up MS0396-E- M [AK4632 MCKPD MCKO PMPLL 2005/06 ...
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... PMSPK bit is “0”, which powers down Speaker-amp. MS0396-E- SPPS BEEPS ALC2S DACA MGAIN0 bit Input Gain 0 0dB 1 +20dB 0 +26dB 1 +32dB Table 26. Input Gain - 46 - [AK4632 DACM MPWR MICAD MGAIN0 Default 2005/06 ...
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... Figure 44. Speaker and Mono Lineout-Amps switch control MS0396-E- SPKG1 MGAIN1 SPKG1-0 bits Gain 00 0dB 01 +2.2dB 10 +4.4dB 11 +8.7dB Table 27. Gain of Speaker-Amp MIX ALC2 ALC1A DACA BEEPA - 47 - [AK4632 SPKG0 BEEPA ALC1M ALC1A ALC2S SPK AOUT 2005/06 ...
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... BICK pin 0 0 MCKI pin 0 1 MCKI pin 1 0 MCKI pin 1 1 MCKI pin 0 0 MCKI pin 0 1 MCKI pin N [AK4632 BCKO1 BCKO0 DIF1 DIF0 BICK Figure See Table 34 Figure 27 Figure 28 Default Figure 29 Default Input Frequency ...
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... BCKP bit Audio Interface Format 0 Figure 23 1 Figure 24 0 Figure 25 1 Figure [AK4632 BCKP FS2 FS1 FS0 Sampling Frequency 8kHz Default 12kHz 16kHz 24kHz 7.35kHz 11.025kHz 14.7kHz 22.05kHz 32kHz 48kHz 29 ...
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... Zero Crossing Timeout Period 8kHz 0 128/fs 16ms 1 256/fs 32ms 0 512/fs 64ms 1 1024/fs 128ms Table 37. Zero Crossing Timeout Period - 50 - [AK4632 WTM1 WTM0 LTM1 LTM0 16kHz Default 31µs 63µs 125µs 250µs 16kHz 8ms ...
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... ADC Input ≥ −6.0dBFS RATT bit GAIN STEP LMAT1 bit LMAT0 bit ATT STEP Table 40. ALC1 Limiter ATT Step Setting - 51 - [AK4632 LMAT1 LMAT0 RATT LMTH Default Default 1 Default ...
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... DATA (HEX) Table 41. Setting Reference Value at ALC1 Recovery Operation MS0396-E- REF6 REF5 REF4 GAIN (dB) STEP 47 +27.5 46 +27.0 45 +26 +19 +0 0.5dB −5.0 06 −5.5 05 −6.0 04 −6.5 03 −7.0 02 −7.5 01 −8 [AK4632 REF3 REF2 REF1 REF0 Default 2005/06 ...
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... Default DVOL7-0: Output Digital Volume (See Table 43) The AK4632 has a digital output volume (256 levels, 0.5dB step, Mute). The gain can be set by the DVOL7-0 bits. The volume is included in front of a DAC block, a input data of DAC is changed from +12 to –115dB with MUTE. This volume has a soft transition function. It takes 1061/fs (=133ms @ fs = 8kHz) or 256/fs (=32ms @ fs = 8kHz) from 00H to FFH ...
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... SAGC1-0: Select Video Output Circuit (See Table 23) MS0396-E- RFS5 RFS4 Volume[dB] Step +19.5 +19.0 +18.5 +18.0 : 0.5dB +0.5 +0.0 -0.5 : -10.5 -11.0 -11.5 -12 SAGC1 SAGC0 VGCA4 [AK4632 RFS3 RFS2 RFS1 RFS0 Default VGCA3 VGCA2 VGCA1 VGCA0 2005/06 ...
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... When the AK4632 is EXT mode (PMPLL bit = “0”), a resistor and capacitor of VCOC pin is not needed. - When the AK4632 is PLL mode (PMPLL bit = “1”), a resistor and capacitor of VCOC pin is shown in Table 45. - Input resistance of AIN pin and Capacitance between MICOUT pin and AIN pin compose of HPF. When the capacitance is 0.22µ ...
Page 56
... The Mic and Beep inputs are single-ended. The input signal range scales with nominally at 0.06 x AVDD Vpp for the Mic input and 0.6 x AVDD Vpp for the Beep input, centered around the internal common voltage (approx. 0.45 x AVDD). Usually the input signal is AC coupled using a capacitor. The cut-off frequency (1/2πRC). The AK4632 can accept input voltages from AVSS to AVDD. ...
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... PLL lock time is 40ms(max) after PMPLL bit changes from “0” to “1” and MCKI is supplied from an external source. (7) The AK4632 starts to output the FCK and BICK clocks after the PLL becomes stable. The normal operation of the block which a clock is necessary for becomes possible. ...
Page 58
... After Power Up: PDN pin “L” → “H” “L” time (1) of 150ns or more is needed to reset the AK4632. (2) DIF1-0, FS3-0, PLL3-0, MSBS and BCKP bits should be set during this period. (3) Power Up VCOM: PMVCM bit = “0” → “1” ...
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... After Power Up: PDN pin “L” → “H” “L” time (1) of 150ns or more is needed to reset the AK4632. (2) DIF1-0, PLL3-0, FS3-0, BCKO1-0, MSBS, BCKP and M/S bits should be set during this period. (3) Power Up VCOM: PMVCM bit = “0” → “1” ...
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... BICK pin <Example> (1) After Power Up: PDN pin “L” → “H” “L” time (1) of 150ns or more is needed to reset the AK4632. (2) DIF1-0 and FS1-0 bits should be set during this period. (3) Power Up VCOM: PMVCM bit = “0” → “1” VCOM should first be powered up before the other block operates. ...
Page 61
... Registers set-up sequence at the ALC1 operation“ At first, clocks should be supplied according to “Clock Set Up” sequence. (1) Set up a sampling frequency (FS3-0 bit). When the AK4632 is PLL mode, MIC and ADC should be powered-up in consideration of PLL lock time after a sampling frequency is changed. ...
Page 62
... SVDD/2 <Example> At first, clocks should be supplied according to “Clock Set Up” sequence. (1) Set up a sampling frequency (FS3-0 bits). When the AK4632 is PLL mode, DAC and Speaker-Amp should be powered-up in consideration of PLL lock time after a sampling frequency is changed. (2) Set up the path of “DAC SPK-Amp” ...
Page 63
... Hi-Z Speaker-Amp” Output Sequence SPK-Amp”: ALC2S bit = “0” SPK-Amp”: BEEPS bit = “0” → “1” SPK-Amp”: BEEPS bit = “1” → “0” [AK4632] Example: (1) Addr:07H, Data:00H (2) Addr:00H, Data:70H (3) Addr:02H, Data:60H (4) Addr:02H, Data:E0H BEEP Signal Output ...
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... Hi-Z <Example> At first, clocks should be supplied according to “Clock Set Up” sequence. (1) Set up a sampling frequency (FS3-0 bits). When the AK4632 is PLL mode, DAC and Mono Line Amp should be powered-up in consideration of PLL lock time after a sampling frequency is changed. (2) Set up the path of “DAC DACA bit: “0” → “1” ...
Page 65
... AOUT pin <Example> At first, clocks should be supplied according to “Clock Set Up” sequence. (1) Set up a sampling frequency (FS3-0 bits). When the AK4632 is PLL mode, DAC and Mono Line Amp should be powered-up in consideration of PLL lock time after a sampling frequency is changed. (2) Set up the path of “DAC ...
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... If any audio functions are not used, VCOM can be powered-down(PMVCM bit =“0”) MS0396-E- (4) (3) Normal Output Figure 55. Video Output Sequence - 66 - [AK4632] Example: Audio Function :No use PLL Master Mode VIDEO Output : DC Output VGCA : 0dB (1) Addr:00H, Data:45H (2) Addr:0CH, Data:02H (3) Addr:01H, Data:8BH Video Output ...
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... Addr:01H, Data:0CH Stop an external MCKI Figure 56. Clock Stopping Sequence (1) Example Audio I/F Format : DSP Mode, BCKP = MSBS = “0” PLL Reference clock: BICK BICK frequency: 64fs Sampling Frequency: 8kHz Figure 57. Clock Stopping Sequence ( [AK4632] (1) Addr:01H, Data:04H (2) Stop the external clocks 2005/06 ...
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... If the clocks are supplied, power down VCOM (PMVCM bit: “1” → “0”) after all blocks except for VCOM are powered-down and a master clock stops. The AK4632 is also powered-down by PDN pin = “L”. When PDN pin = “L”, the registers are initialized. ...
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... M AB 0.08 Note) The exposed pad on the bottom surface of the package must be open. Material & Lead finish Package molding compound: Lead frame material: Lead frame surface treatment: MS0396-E-00 PACKAGE 0.40 ± 0. C0. Epoxy Cu Solder (Pb free) plate - 69 - [AK4632] Exposed Pad 32 1 3.5 2005/06 ...
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... AKM harmless from any and all claims arising from the use of said product in the absence of such notification. MS0396-E-00 MARKING 4632 XXXX 1 XXXX : Date code identifier (4 digits) Revision History Page Contents IMPORTANT NOTICE - 70 - [AK4632] 2005/06 ...